| Patent Number |
Title Of Patent |
Date Issued |
| 7433951 |
System and method for controlling resource revocation in a multi-guest computer system |
October 7, 2008 |
| At least one guest system, for example, a virtual machine, is connected to a host system, which includes a system resource such as system machine memory. Each guest system includes a guest operating system (OS). A resource requesting mechanism, preferably a driver, is installed within |
| 7428636 |
Selective encryption system and method for I/O operations |
September 23, 2008 |
| Upon occurrence of a trigger condition, writes of allocation units of data (including code) to a device, such as writes of blocks to a disk, are first encrypted. Each allocation unit is preferably a predetermined integral multiple number of minimum I/O units. A data structure is marked |
| 7412492 |
Proportional share resource allocation with reduction of unproductive resource consumption |
August 12, 2008 |
| Units of a resource are allocated among a plurality of clients by a system-level management module using a proportional share resource allocation scheme. For each client, a metric is evaluated that is a function both of a non-usage-based, client-specific factor and of a usage-based f |
| 7260820 |
Undefeatable transformation for virtual machine I/O operations |
August 21, 2007 |
| I/O operations between a virtual machine (VM) and a device external to the VM are monitored by a virtual machine monitor (VMM). Data passing between the VM and the external device is transformed by the VMM, in some cases only when a predetermined filtering or triggering condition is met. |
| 6961930 |
Efficient, transparent and flexible latency sampling |
November 1, 2005 |
| The performance of an executing computer program on a computer system is monitored using latency sampling. The program has object code instructions and is executing on the computer system. At intervals, the execution of the computer program is interrupted including delivering a first |
| 6880022 |
Transparent memory address remapping |
April 12, 2005 |
| A computer has a hardware memory arranged into portions that are separately addressable using first identifiers, which are represented using a first number of address bits. A subsystem that is able to address a second space of the hardware memory using second identifiers initiates I/O re |
| 6789156 |
Content-based, transparent sharing of memory units |
September 7, 2004 |
| A computer system has one or more software context that share use of a memory that is divided into units such as pages. In the preferred embodiment of the invention, the context are, or include, virtual machines running on a common hardware platform. The context, as opposed to merely |
| 6725289 |
Transparent address remapping for high-speed I/O |
April 20, 2004 |
| A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory region. Requests for memory are mapped at least once, for example from virtual to physical page |
| 6609208 |
Energy-based sampling for performance monitoring |
August 19, 2003 |
| The present invention performs energy usage profiling of computing resources using an energy-based interrupt source for sampling. The present invention uses energy consumption as an event to be monitored by specialized profiling hardware. An energy consumption counter tracks the ener |
| 6549930 |
Method for scheduling threads in a multithreaded processor |
April 15, 2003 |
| A method is provided for scheduling execution of a plurality of threads executed in a multithreaded processor. Resource utilizations of each of the plurality of threads are measured while the plurality of threads are concurrently executing in the multithreaded processor. Each of the |
| 6442585 |
Method for scheduling contexts based on statistics of memory system interactions in a computer s |
August 27, 2002 |
| A method schedules execution contexts in a computer system based on memory interactions. The computer system includes a processor and a hierarchical memory arranged in a plurality of levels. Memory transactions are randomly sampled for a plurality of contexts. The contexts can be threads |
| 6374367 |
Apparatus and method for monitoring a computer system to guide optimization |
April 16, 2002 |
| A method for sampling the performance of a computer system is provided. The computer system includes a plurality of functional units. The method selects transactions to be processed by a particular functional unit of the computer system. State information is stored while the selected |
| 6332178 |
Method for estimating statistics of properties of memory system transactions |
December 18, 2001 |
| A method estimates statistics of properties of transactions processed by a memory sub-system of a computer system. The method randomly selects memory transactions processed by the memory sub-system. States of the system are recorded as samples while the selected transaction are processed |
| 6237059 |
Method for estimating statistics of properties of memory system interactions among contexts in a |
May 22, 2001 |
| A method analyzes memory transaction processed by memories of a computer system. The method selects a set of addresses of the memories. State information from a plurality of consecutive predetermined memory transactions to the selected addresses are recorded while the selected transa |
| 6202127 |
Apparatus for spatial and temporal sampling in a computer memory system |
March 13, 2001 |
| An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a selector for selecting memory transactions based on first state and transaction information. T |
| 6195748 |
Apparatus for sampling instruction execution information in a processor pipeline |
February 27, 2001 |
| An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. E |
| 6175814 |
Apparatus for determining the instantaneous average number of instructions processed |
January 16, 2001 |
| An apparatus is provided for determining an average number of instructions entering a stage of a processor pipeline of a computer system during a clock cycle of a processor clock. The number of instructions entering a particular stage of the pipeline are stored in a queue during each of |
| 6163840 |
Method and apparatus for sampling multiple potentially concurrent instructions in a processor pi |
December 19, 2000 |
| An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A |
| 6148396 |
Apparatus for sampling path history in a processor pipeline |
November 14, 2000 |
| An apparatus is provided for collecting state information associated with an execution path of recently processed instructions in a processor pipeline of a computer system. The apparatus identifies a class of instructions to be sampled. Path-identifying state information of a current |
| 6119075 |
Method for estimating statistics of properties of interactions processed by a processor pipeline |
September 12, 2000 |
| Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A set of instructions are r |
| 6092180 |
Method for measuring latencies by randomly selected sampling of the instructions while the instr |
July 18, 2000 |
| In a method for scheduling instructions executed in a computer system including a processor and a memory subsystem, pipeline latencies and resource utilization are measured by sampling hardware while the instructions are executing. The instructions are then scheduled according to the |
| 6070009 |
Method for estimating execution rates of program execution paths |
May 30, 2000 |
| A method is provided for estimating execution rates of program executions paths. The method samples path-identifying state information of selected instructions while executing the program in a processor. A control flow graph of the program is supplied, the control flow graph includes a |
| 6000044 |
Apparatus for randomly sampling instructions in a processor pipeline |
December 7, 1999 |
| An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are iden |
| 5964867 |
Method for inserting memory prefetch operations based on measured latencies in a program optimiz |
October 12, 1999 |
| A method is provided for optimizing a program by inserting memory prefetch operations in the program executing in a computer system. The computer system includes a processor and a memory. Latencies of instructions of the program are measured by hardware while the instructions are process |
| 5923872 |
Apparatus for sampling instruction operand or result values in a processor pipeline |
July 13, 1999 |
| An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Any one of the fetched instructions are identified as a par |
| 5809450 |
Method for estimating statistics of properties of instructions processed by a processor pipeline |
September 15, 1998 |
| A method is provided for estimating statistics of properties of instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Some of the fetched instructions are randomly |
| 5796939 |
High frequency sampling of processor performance counters |
August 18, 1998 |
| In a computer system, an apparatus is configured to collect performance data of a computer system including a plurality of processors for concurrently executing instructions of a program. A plurality of performance counters are coupled to each processor. The performance counters stor |
