| Patent Number |
Title Of Patent |
Date Issued |
| RE37505 |
Stacked capacitor construction |
January 15, 2002 |
| A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reac |
| 7366946 |
ROM redundancy in ROM embedded DRAM |
April 29, 2008 |
| Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or registers with ROM data which is read instead of erroneous data. Multiple identical arrays of ROM bits can also be used for redu |
| 7218547 |
ROM embedded DRAM with anti-fuse programming |
May 15, 2007 |
| A ROM embedded DRAM provides ROM cells that can be electrically programmed to a data state using DRAM capacitor memory cells. Numerous techniques for reading the memory cells are provided if a single state memory is desired. For example, bias techniques allow un-programmed ROM cells to b |
| 7174477 |
ROM redundancy in ROM embedded DRAM |
February 6, 2007 |
| Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or registers with ROM data which is read instead of erroneous data. Multiple identical arrays of ROM bits can also be used for redu |
| 7099212 |
Embedded ROM device using substrate leakage |
August 29, 2006 |
| A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias |
| 7012006 |
Embedded ROM device using substrate leakage |
March 14, 2006 |
| A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias |
| 7001816 |
Embedded ROM device using substrate leakage |
February 21, 2006 |
| A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias |
| 6996021 |
ROM embedded DRAM with bias sensing |
February 7, 2006 |
| A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitr |
| 6903957 |
Half density ROM embedded DRAM |
June 7, 2005 |
| A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data states are stored. Two word lines are used to access the memory cell pair. Because one of th |
| 6865130 |
ROM embedded DRAM with bias sensing |
March 8, 2005 |
| A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitr |
| 6865100 |
6F2 architecture ROM embedded DRAM |
March 8, 2005 |
| A read only memory (ROM) embedded dynamic random access memory (DRAM) has a 6F.sup.2 architecture and uses isolation gates as hard shorting connections for ground or supply voltage connections to program ROM bits within the ROM embedded DRAM. |
| 6852611 |
ROM embedded DRAM with dielectric removal/short |
February 8, 2005 |
| A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper conductor and dielectric are removed |
| 6825095 |
Methods of forming capacitors |
November 30, 2004 |
| The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic |
| 6788603 |
ROM embedded DRAM with bias sensing |
September 7, 2004 |
| A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitr |
| 6785167 |
ROM embedded DRAM with programming |
August 31, 2004 |
| Programming efficiency of a read only memory (ROM) embedded dynamic random access memory (DRAM) is improved by programming only one polarity of bits in non-volatile cells of the ROM embedded DRAM, and then blanket programming volatile cells in the ROM embedded DRAM to represent the r |
| 6781867 |
Embedded ROM device using substrate leakage |
August 24, 2004 |
| A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias |
| 6771529 |
ROM embedded DRAM with bias sensing |
August 3, 2004 |
| A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitr |
| 6768664 |
ROM embedded DRAM with bias sensing |
July 27, 2004 |
| A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitr |
| 6753617 |
Method for improving a stepper signal in a planarized surface over alignment topography |
June 22, 2004 |
| A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises |
| 6747889 |
Half density ROM embedded DRAM |
June 8, 2004 |
| A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data states are stored. Two word lines are used to access the memory cell pair. Because one of th |
| 6737730 |
High-pressure anneal process for integrated circuits |
May 18, 2004 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contr |
| 6735108 |
ROM embedded DRAM with anti-fuse programming |
May 11, 2004 |
| A ROM embedded DRAM provides ROM cells that can be electrically programmed to a data state using DRAM capacitor memory cells. Numerous techniques for reading the memory cells are provided if a single state memory is desired. For example, bias techniques allow un-programmed ROM cells to b |
| 6731556 |
DRAM with bias sensing |
May 4, 2004 |
| A DRAM improves cell read margins using bias, or reference, circuitry. The reference circuitry is coupled to a complimentary digit line to improve a differential voltage with an active digit line. One embodiment, improves one's margin by decreasing the complimentary digit line voltage. T |
| 6710390 |
Capacitors and DRAM arrays |
March 23, 2004 |
| The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic |
| 6703327 |
High-pressure anneal process for integrated circuits |
March 9, 2004 |
| An improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the fina |
| 6703326 |
High-pressure anneal process for integrated circuits |
March 9, 2004 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the cont |
| 6703325 |
High pressure anneal process for integrated circuits |
March 9, 2004 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contr |
| 6693048 |
High-pressure anneal process for integrated circuits |
February 17, 2004 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contr |
| 6673726 |
High-pressure anneal process for integrated circuits |
January 6, 2004 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contr |
| 6670289 |
High-pressure anneal process for integrated circuits |
December 30, 2003 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the cont |
| 6665207 |
ROM embedded DRAM with dielectric removal/short |
December 16, 2003 |
| A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper conductor and dielectric are removed |
| 6603693 |
DRAM with bias sensing |
August 5, 2003 |
| A DRAM improves cell read margins using bias, or reference, circuitry. The reference circuitry is coupled to a complimentary digit line to improve a differential voltage with an active digit line. One embodiment, improves one's margin by decreasing the complimentary digit line voltage. T |
| 6545899 |
ROM embedded DRAM with bias sensing |
April 8, 2003 |
| A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitr |
| 6501188 |
Method for improving a stepper signal in a planarized surface over alignment topography |
December 31, 2002 |
| A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises |
| 6492285 |
High-pressure anneal process for integrated circuits |
December 10, 2002 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contr |
| 6472328 |
Methods of forming an electrical contact to semiconductive material |
October 29, 2002 |
| A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer |
| 6455400 |
Semiconductor processing methods of forming silicon layers |
September 24, 2002 |
| In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550.degree. C. to about 560.d |
| 6407455 |
Local interconnect using spacer-masked contact etch |
June 18, 2002 |
| A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface and a conductive runner extends over the active area such that a lower surface of the co |
| 6391805 |
High-pressure anneal process for integrated circuits |
May 21, 2002 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contr |
| 6387828 |
High-pressure anneal process for integrated circuits |
May 14, 2002 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contr |
| 6383887 |
Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits |
May 7, 2002 |
| The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic |
| 6352946 |
High-pressure anneal process for integrated circuits |
March 5, 2002 |
| This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contr |
| 6309941 |
Methods of forming capacitors |
October 30, 2001 |
| The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic |
| 6306705 |
Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits |
October 23, 2001 |
| The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic |
| 6281131 |
Methods of forming electrical contacts |
August 28, 2001 |
| A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer |
| 6242816 |
Method for improving a stepper signal in a planarized surface over alignment topography |
June 5, 2001 |
| A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises |
| 6207523 |
Methods of forming capacitors DRAM arrays, and monolithic integrated circuits |
March 27, 2001 |
| The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic |
| 6180485 |
Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits |
January 30, 2001 |
| The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic |
| 6166395 |
Amorphous silicon interconnect with multiple silicon layers |
December 26, 2000 |
| In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550.degree. C. to about 560.d |
| 6153527 |
Semiconductor processing method of making electrical contact to a node received within a mass of |
November 28, 2000 |
| A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in |
