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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Voldman; Steven Howard
Address:
South Burlington, VT
No. of patents:
38
Patents:












Patent Number Title Of Patent Date Issued
8193563 High power device isolation and integration June 5, 2012
A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric iso
8178925 Semiconductor diode structure operation method May 15, 2012
A semiconductor structure operation method. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and
8143671 Lateral trench FETs (field effect transistors) March 27, 2012
A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, a second g
8110875 Structure for charge dissipation during fabrication of integrated circuits and isolation thereof February 7, 2012
A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a t
8017995 Deep trench semiconductor structure and method September 13, 2011
An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate.
7872334 Carbon nanotube diodes and electrostatic discharge circuits and methods January 18, 2011
Diodes and method of fabricating diodes. A diode includes: an p-type single wall carbon nanotube; an n-type single wall carbon nanotube, the p-type single wall carbon nanotube in physical and electrical contact with the n-type single wall carbon nanotube; and a first metal pad in phy
7781292 High power device isolation and integration August 24, 2010
A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric iso
7709924 Semiconductor diode structures May 4, 2010
A semiconductor structure and a method for operating the same. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact w
7541247 Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral dou June 2, 2009
A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transist
7309898 Method and apparatus for providing noise suppression in an integrated circuit December 18, 2007
A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.
7020857 Method and apparatus for providing noise suppression in a integrated circuit March 28, 2006
A method and apparatus for analyzing an integrated circuit design for pnpn structures which are likely to latchup or cause injection of noise into the substrate. Once qualifying pnpn structures are identified, the method and apparatus automatically inserts a noise and latchup suppression
6826025 Method and apparatus for providing ESD protection and/or noise reduction in an integrated circui November 30, 2004
An integrated circuit having either or both ESD and noise suppression devices that use the inherent resistance in the substrate as an ESD trigger and/or part of the noise suppression.
6774017 Method and structures for dual depth oxygen layers in silicon-on-insulator processes August 10, 2004
A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the tre
6762918 Fault free fuse network July 13, 2004
A fuse state circuit for reading the state of a fuse that is enhanced to reduce the circuits susceptibility to ESD, EOS or CDM events.
6720637 SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral April 13, 2004
An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the
6710983 ESD protection for GMR sensors of magnetic heads using SiGe integrated circuit devices March 23, 2004
A magnetic head includes a GMR read head that is protected from electrostatic discharge (ESD) on a slider by a silicon germanium (SiGe) integrated circuit device. In a preferred embodiment the SiGe circuit device includes one or more silicon germanium heterojunction bipolar transisto
6635548 Capacitor and method for forming same October 21, 2003
A method of forming an integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the method includes depositing a first insulator layer over an interconnect level surface of a semiconductor substrate having active devices. First and second conductive l
6552879 Variable voltage threshold ESD protection April 22, 2003
An ESD protective circuit is described which has a very low, variable turn-on threshold by using a shunting MOSFET which has an isolated substrate/body which is connected to an electrode that is provided in addition to the gate, source and drain electrodes. A variable gate voltage wh
6552406 SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral April 22, 2003
An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the
6549061 Electrostatic discharge power clamp circuit April 15, 2003
An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that
6476445 Method and structures for dual depth oxygen layers in silicon-on-insulator processes November 5, 2002
A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the tre
6465870 ESD robust silicon germanium transistor with emitter NP-block mask extrinsic base ballasting res October 15, 2002
A ESD (electrostatic discharge) robust SiGe bipolar transistor is provided which comprises a substrate of a first conductivity type; a doped subcollector region of a second conductivity type formed on the substrate, the doped subcollector region including an epitaxial collector region
6429489 Electrostatic discharge power clamp circuit August 6, 2002
A SiGe ESD power clamp in a Darlington type configuration where the trigger device has a collector-to-emitter breakdown voltage (BVCEO) that is lower than that of the clamping device, and a frequency cutoff that is higher than that of the clamping device.
6410962 Structure for SOI wafers to avoid electrostatic discharge June 25, 2002
A method of dissipating charge from a substrate of an SOI device is provided wherein a charge dissipation path is formed in the device so that it abuts the various layers thereof. Exemplary charge dissipation paths include high conductive materials, resistive means, and field emission or
6384468 Capacitor and method for forming same May 7, 2002
An integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the capacitor includes a first insulator layer overlying an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are provided in th
6294419 Structure and method for improved latch-up using dual depth STI with impurity implant September 25, 2001
A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at
6281593 SOI MOSFET body contact and method of fabrication August 28, 2001
A body contact to a SOI device is created by providing a deeper buried oxide region for providing connection to the FET body.
6245600 Method and structure for SOI wafers to avoid electrostatic discharge June 12, 2001
A method of dissipating charge from a substrate of an SOI device is provided wherein a charge dissipation path is formed in the device so that it abuts the various layers thereof. Exemplary charge dissipation paths include high conductive materials, resistive means, and field emission or
6229372 Active clamp network for multiple voltages May 8, 2001
An active clamp circuit for digital circuits includes a first MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the g
6144086 Structure for improved latch-up using dual depth STI with impurity implant November 7, 2000
A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at
6097068 Semiconductor device fabrication method and apparatus using connecting implants August 1, 2000
A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within th
6074899 3-D CMOS-on-SOI ESD structure and method June 13, 2000
Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.
6057184 Semiconductor device fabrication method using connecting implants May 2, 2000
A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within th
5923067 3-D CMOS-on-SOI ESD structure and method July 13, 1999
Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.
5712747 Thin film slider with on-board multi-layer integrated circuit January 27, 1998
A thin film slider with an on-board multi-layer integrated circuit includes a substrate with an air bearing surface and a substantially parallel upper surface spanned by a deposit end. A magnetic head being formed at the deposit end, positioned to magnetically exchange data with a magnet
5710682 Electrostatic discharge protection system for MR heads January 20, 1998
An MR head receives ESD protection from a mechanism that automatically and releasably shorts the MR head whenever a suspension assembly on which the head is mounted is not installed in an HDA. The suspension assembly includes a flexure underlying a load beam, which is connected to an
5656553 Method for forming a monolithic electronic module by dicing wafer stacks August 12, 1997
A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The
5644454 Electrostatic discharge protection system for MR heads July 1, 1997
An MR head receives ESD protection from a mechanism that automatically and releasably shorts the MR head whenever a suspension assembly on which the head is mounted is not installed in an HDA. The suspension assembly includes a flexure underlying a load beam, which is connected to an










 
 
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