| Patent Number |
Title Of Patent |
Date Issued |
| 8164942 |
High performance eDRAM sense amplifier |
April 24, 2012 |
| Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digit |
| 8010066 |
Digital transmission circuit and interface providing selectable power consumption via multiple w |
August 30, 2011 |
| A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is prov |
| 7636556 |
Digital transmission circuit and method providing selectable power consumption via multiple weig |
December 22, 2009 |
| A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and |
| 7522670 |
Digital transmission circuit and method providing selectable power consumption via single-ended |
April 21, 2009 |
| A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver s |
| 7443195 |
Method of transparently reducing power consumption of a high-speed communication link |
October 28, 2008 |
| A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolat |
| 7394276 |
Active cancellation matrix for process parameter measurements |
July 1, 2008 |
| An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices |
| 7353007 |
Digital transmission circuit and method providing selectable power consumption via multiple weig |
April 1, 2008 |
| A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided |
| 7269397 |
Method and apparatus for measuring communications link quality |
September 11, 2007 |
| A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data |
| 7133654 |
Method and apparatus for measuring communications link quality |
November 7, 2006 |
| A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data |
| 6812739 |
Method of transparently reducing power consumption of a high-speed communication link |
November 2, 2004 |
| A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolat |
| 6801025 |
Method and apparatus for control of voltage regulation |
October 5, 2004 |
| According to an apparatus form of the invention, integrated circuitry on a single chip includes a bit-programmable voltage regulator supplying voltage to first circuitry on the chip. The integrated circuitry also includes second circuitry operable for characterizing performance of the |
| 6710668 |
Glitchless wide-range oscillator, and method therefor |
March 23, 2004 |
| According to an apparatus form of the invention, oscillator circuitry for operating a number of inverters in a loop (also known as a "ring") includes a number of inverters. The inverters include a series of M inverters and a series of N inverters. The M inverters have signal propagat |
| 6621358 |
Differential voltage controlled oscillator, and method therefor |
September 16, 2003 |
| In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. |
| 5900740 |
System and method for adjusting a voltage |
May 4, 1999 |
| First current is conducted through a first path to adjust a voltage at a node toward a predetermined level in response to the voltage being within a first subrange of voltages. Second current is conducted through a second path to adjust the voltage at the node toward the predetermined le |
