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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Verma; Purakh Raj
Address:
Singapore, SG
No. of patents:
27
Patents:












Patent Number Title Of Patent Date Issued
8288235 Self-aligned body fully isolated device October 16, 2012
A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a fin
8222130 High voltage device July 17, 2012
A method of forming a device is presented. The method includes providing a substrate prepared with an active device region. The active device region includes gate stack layers of a gate stack including at least a gate electrode layer over a gate dielectric layer. A first mask is prov
8138051 Integrated circuit system with high voltage transistor and method of manufacture thereof March 20, 2012
A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by a
7994563 MOS varactors with large tuning range August 9, 2011
A device is presented. The device includes a substrate with a first well of a first polarity type. The first well defines a varactor region and comprises a lower first well boundary located above a bottom surface of the substrate. A second well in the varactor region is also included in
7951680 Integrated circuit system employing an elevated drain May 31, 2011
A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above
7867862 Semiconductor structure including high voltage device January 11, 2011
A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first
7846805 Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process December 7, 2010
A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurit
7824968 LDMOS using a combination of enhanced dielectric stress layer and dummy gates November 2, 2010
First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodime
7618873 MOS varactors with large tuning range November 17, 2009
A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the
7410874 Method of integrating triple gate oxide thickness August 12, 2008
A method for forming TGO structures includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the
7382027 MOSFET device with low gate contact resistance June 3, 2008
A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavi
7326609 Semiconductor device and fabrication method February 5, 2008
A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the sec
7268412 Double polysilicon bipolar transistor September 11, 2007
A bipolar transistor with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emi
7238971 Self-aligned lateral heterojunction bipolar transistor July 3, 2007
A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed p
7049201 Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy May 23, 2006
A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the
7022578 Heterojunction bipolar transistor using reverse emitter window April 4, 2006
A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitter structure, an i
6972237 Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial gr December 6, 2005
A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector
6936519 Double polysilicon bipolar transistor and method of manufacture therefor August 30, 2005
A bipolar transistor, and manufacturing method therefor, with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector regio
6933188 Use of a selective hard mask for the integration of double diffused drain MOS devices in deep su August 23, 2005
A process for integrating the fabrication of double diffused drain (DDD) MOSFET devices with the fabrication sub-micron CMOS devices, has been developed. The process features formation of an insulator hard mask shape on an underlying polysilicon gate structure shape in the DDD MOSFET
6924202 Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact August 2, 2005
A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector regio
6908824 Self-aligned lateral heterojunction bipolar transistor June 21, 2005
A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a c
6861317 Method of making direct contact on gate by using dielectric stop layer March 1, 2005
A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavi
6835631 Method to enhance inductor Q factor by forming air gaps below inductors December 28, 2004
A method of enhancing inductor performance comprising the following steps. A structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The
6638844 Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semi October 28, 2003
A method of reducing substrate coupling and noise for one or more RFCMOS components comprising the following steps. A substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolation structures are formed within t
6486017 Method of reducing substrate coupling for chip inductors by creation of dielectric islands by se November 26, 2002
A new method is provided for the creation of a horizontal spiral inductor over the surface of a silicon substrate. A first layer of dielectric is deposited over the surface of the substrate, this first layer of dielectric is patterned and etched creation islands of first dielectric m
6372652 Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage April 16, 2002
A method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to
5716880 Method for forming vertical polysilicon diode compatible with CMOS/BICMOS formation February 10, 1998
A method for forming a diode for use within an integrated circuit, and a diode formed through the method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a dielectric layer. There is then formed upon the dielectric layer a first










 
 
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