| Patent Number |
Title Of Patent |
Date Issued |
| 6174759 |
Method of manufacturing a semiconductor device |
January 16, 2001 |
| In the manufacture of integrated circuits with an embedded non-volatile memory, it is known to first provide the greater part of the memory and subsequently provide the CMOS logic in a second series of steps of a standard CMOS process. By virtue of this separation of process steps, it |
| 6069033 |
Method of manufacturing a non-volatile memory and a CMOS transistor |
May 30, 2000 |
| The invention provides a method of combining an EPROM (or EEPROM) with a standard CMOS process. After growing the gate oxide 9, a lightly doped polycrystalline or amorphous silicon layer 10, hereinafter referred to as poly I, is deposited. In this layer, the floating gate 13 of the memor |
| 5879990 |
Semiconductor device having an embedded non-volatile memory and method of manufacturing such a s |
March 9, 1999 |
| The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first |
| 5371027 |
Method of manufacturing a semiconductor device having a non-volatile memory with an improved tun |
December 6, 1994 |
| Very thin tunnel oxides are used in conventional non-volatile memories to obtain a sufficiently strong tunnelling current to or from the floating gate. Usual thicknesses of the tunnel oxide lie in the 8-10 nm range.The invention renders it possible to use tunnel oxides of a much greater |
| 5358902 |
Method of producing conductive pillars in semiconductor device |
October 25, 1994 |
| Electrical connection is provided to a device region (3,4) bounded by an insulating region (12a,12b,9) and adjacent one major surface (1a) of a semiconductor body (1) by applying a flowable organic material to form an organic layer (20) on the one major surface (1a), defining a masking l |
| 5316966 |
Method of providing mask alignment marks |
May 31, 1994 |
| A method of manufacturing mask alignment marks on an active surface of a semiconductor substrate (12) is disclosed, in which first, at least one layer (13) of a material resistant to oxidation is formed on the active surface, after which by a local etching of this layer, zones (15') for |
| 5063169 |
Selectively plating conductive pillars in manufacturing a semiconductor device |
November 5, 1991 |
| Electrical connection to a device region (3,4) of a semiconductor device is formed by providing a semiconductor body (1) having adjacent one major surface (12) a device region (3,4) bounded by an insulating region (19a,19b,9), providing an activating layer (11) on the one major surface |
| 5015599 |
Method of manufacturing a device comprising MIS transistors having a projecting gate on the weak |
May 14, 1991 |
| Method is set forth of manufacturing a device comprising MIS transistors having a projecting gate on the weakly doped parts of source and drain regions.A method comprising the deposition of a first and a second polycrystalline conducting layer, which are separated by an insulating layer. |
| 5015598 |
Method of manufacturing a device comprising MIS transistors having a gate electrode in the form |
May 14, 1991 |
| A method is set forth comprising the deposition of a first and a second polycrystalline conducting layer, which are separated by an insulating layer, with the object of creating gate islands which extend in the direction of highly doped parts (22b, 23b) of source and drain zones. Acc |
| 4489357 |
Magnetic sensor having multilayered flux conductors |
December 18, 1984 |
| A magnetic sensor (1) includes a magneto-resistive element (3) which magnetically bridges a gap (15) between two magnetic flux conductors (6,7). In order to reduce the noise level and higher harmonic distortion of the sensor, each of the flux conductors (6,7) includes at least two la |
