| Patent Number |
Title Of Patent |
Date Issued |
| 8037337 |
Structures including circuits for noise reduction in digital systems |
October 11, 2011 |
| A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is |
| 7831935 |
Method and architecture for power management of an electronic device |
November 9, 2010 |
| A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between |
| 7715995 |
Design structure for measurement of power consumption within an integrated circuit |
May 11, 2010 |
| An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data sign |
| 7463083 |
Noise reduction in digital systems when the noise is caused by simultaneously clocking data regi |
December 9, 2008 |
| A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data a |
| 7454642 |
Method and architecture for power management of an electronic device |
November 18, 2008 |
| A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between |
| 7317348 |
Noise reduction in digital systems |
January 8, 2008 |
| A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit |
| 7135907 |
Clock signal distribution utilizing differential sinusoidal signal pair |
November 14, 2006 |
| A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and c |
| 7080344 |
Coding of FPGA and standard cell logic in a tiling structure |
July 18, 2006 |
| A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect's type. The lang |
| 7071757 |
Clock signal distribution utilizing differential sinusoidal signal pair |
July 4, 2006 |
| A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and c |
| 6944698 |
Method and apparatus for providing bus arbitrations in a data processing system |
September 13, 2005 |
| A method and apparatus for providing bus arbitrations in a multiprocessor system is disclosed. A computer system includes a common bus that is shared by multiple cores, such as processors. A history of bus requests for the common bus made by the cores is stored in a bus request history |
| 6934656 |
Auto-linking of function logic state with testcase regression list |
August 23, 2005 |
| A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and cre |
| 6834353 |
Method and apparatus for reducing power consumption of a processing integrated circuit |
December 21, 2004 |
| In a first aspect, a method is provided for conserving power in a processing integrated circuit. The method includes the steps of (1) calculating power consumption for executing an instruction and data corresponding to the instruction; and (2) executing the instruction if such execut |
| 6820254 |
Method and system for optimizing code using an optimizing coprocessor |
November 16, 2004 |
| A data processing system includes a central processing unit (CPU) in communication with a system memory. Within the system memory, there is stored legacy code that does not utilize the full features of the CPU. The data processing system also includes a code-optimizing coprocessor in |
| 6479974 |
Stacked voltage rails for low-voltage DC distribution |
November 12, 2002 |
| A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power |
| 6477654 |
Managing VT for reduced power using power setting commands in the instruction stream |
November 5, 2002 |
| An integrated circuit includes a plurality of functional units which are capable of operating at more than one power/performance level and a power control unit. The power control unit controls the power/performance consumption of the different functional units to optimize operation of th |
| 6425109 |
High level automatic core configuration |
July 23, 2002 |
| A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure |
| 6345362 |
Managing Vt for reduced power using a status table |
February 5, 2002 |
| An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit |
| 6141351 |
Radio frequency bus for broadband microprocessor communications |
October 31, 2000 |
| Disclosed is a system for providing broader bandwidth in microprocessor bus, board and system designs. Broader bandwidth is achieved by dividing the full spectrum of frequencies available into discrete bandwidth packages, much like radio communications. The system includes a bus that |
| 6119241 |
Self regulating temperature/performance/voltage scheme for micros (X86) |
September 12, 2000 |
| A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that th |
| 6026471 |
Anticipating cache memory loader and method |
February 15, 2000 |
| According to the present invention, an anticipating cache memory loader is provided to "pre-load" the cache with the data and instructions most likely to be needed by the CPU once the currently executing task is completed or interrupted. The data and instructions most likely to be ne |
| 5986962 |
Internal shadow latch |
November 16, 1999 |
| An integrated circuit implements simple and efficient normal power to low power and low power to normal power transitions. Dedicated shadow latch circuits are added, each having a corresponding system latch. The state of the system latches is transferred to the shadow latches upon a tran |
| 5874833 |
True/complement output bus for reduced simulataneous switching noise |
February 23, 1999 |
| A true/complement integrated circuit device is disclosed for reducing an amount of simultaneous switching on a bus between a current state and a next state. The device includes a current state register connected to the bus for outputting the current state onto the bus during a first cloc |
| 5832284 |
Self regulating temperature/performance/voltage scheme for micros (X86) |
November 3, 1998 |
| A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that th |
