Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Venkatraman; Prasad
Address:
Gilbert, AZ
No. of patents:
24
Patents:












Patent Number Title Of Patent Date Issued
8207035 Method of forming an integrated power device and structure June 26, 2012
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
8138033 Semiconductor component and method of manufacture March 20, 2012
A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semic
8048740 Vertical MOS transistor and method therefor November 1, 2011
In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor.
8035161 Semiconductor component October 11, 2011
A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provide
8034685 Semiconductor component and method of manufacture October 11, 2011
A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches
8021947 Method of forming an insulated gate field effect transistor device having a shield electrode str September 20, 2011
In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming disposable dielectric stack overlying a substrate. The method also includes forming the trench regions adjacent to the disposab
7939897 Method of forming a low resistance semiconductor contact and structure therefor May 10, 2011
In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.
7915672 Semiconductor device having trench shield electrode structure March 29, 2011
In one embodiment, a structure for a semiconductor device having a trench shield electrode includes a control pad, control runners, shield runners, and a control/shield electrode contact structure. The structure is configured to use a single level of metal to connect the various comp
7851852 Method of forming a low capacitance semiconductor device and structure therefor December 14, 2010
In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
7767529 Semiconductor component and method of manufacture August 3, 2010
A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provide
7736984 Method of forming a low resistance semiconductor contact and structure therefor June 15, 2010
In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.
7714381 Method of forming an integrated power device and structure May 11, 2010
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
7652329 Vertical MOS transistor and method therefor January 26, 2010
In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor.
7619287 Method of forming a low capacitance semiconductor device and structure therefor November 17, 2009
In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
7538370 Semiconductor device having reduced gate charge and reduced on resistance and method May 26, 2009
In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type
7192814 Method of forming a low capacitance semiconductor device and structure therefor March 20, 2007
In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
7189608 Semiconductor device having reduced gate charge and reduced on resistance and method March 13, 2007
In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type
6987040 Trench MOSFET with increased channel density January 17, 2006
A MOSFET device (50) has a trench (60) extending from a major surface (56) of the device (50). Within the trench (60), a gate structure (62) is formed where the top surface (64) is below the major surface (56). Source regions (66, 68) are formed along a vertical wall (84) inside of the
6982193 Method of forming a super-junction semiconductor device January 3, 2006
In one embodiment, a transistor is formed to have alternating depletion and conduction regions that are formed by doping the depletion and conduction regions through an opening in a substrate of the transistor.
6870221 Power switching transistor with low drain to gate capacitance March 22, 2005
A transistor (10) is formed on a semiconductor substrate (12) with a first surface (19) for forming a channel (40). A gate dielectric (22) has a first thickness overlying a first portion of the channel, and a dielectric film (20) overlies a second portion of the channel and has a second
6852634 Low cost method of providing a semiconductor device having a high channel density February 8, 2005
A method of making a semiconductor device 10 by forming a first dielectric layer 140 on a substrate, etching through the first dielectric layer to form a trench 150 having a channel region 135 on a sidewall 160 of the trench, and laterally removing a portion of the first dielectric layer
6818946 Trench MOSFET with increased channel density November 16, 2004
A MOSFET device (50) has a trench (60) extending from a major surface (56) of the device (50). Within the trench (60), a gate structure (62) is formed where the top surface (64) is below the major surface (56). Source regions (66,68) are formed along a vertical wall (84) inside of the tr
6344379 Semiconductor device with an undulating base region and method therefor February 5, 2002
A transistor (30) uses a single continuous base region (40) with an undulating structure. The semiconductor device is an insulated gate field effect transistor having a semiconductor substrate with a plurality of doped base branches, which extend into the semiconductor substrate, form
5897343 Method of making a power switching trench MOSFET having aligned source regions April 27, 1999
A trench power switching transistor (10) is fabricated having sub-micron features on a body layer (26) without using sub-micron lithography. An opening in a field oxide layer (28) defines an area for implanting a source region (30) in the body layer (26) that is self-aligned to a first










 
 
  Recently Added Patents
System and method for customized prompting
Notebook computer
Systems and methods for vehicle cruise control
Cell proliferation inhibitor
Compounds for nonsense suppression and methods for their use
Electrophoresis display having touch screen and method for driving the touch screen
Policy based cryptographic application programming interface in secure memory
  Randomly Featured Patents
Container storage organizer
Interface switching apparatus and switching control method
Bidet with separate units for washing the anal region, pudendal region and oral cavity
Method of organizing and analyzing field warranty data
Medium for electrophoresis
Soybean agrobacterium transformation method
Electrophoretic medium for electrophoretic separation, gel holder for holding the same medium, slab type electrophoretic apparatus using the same medium and gel holder, and electrophoretic gel
Diffusing evaporator of active substances
Mobile telephone holder
Apparatus for scanning an original