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Inventor:
Veliadis; John V.
Address:
Midlothian, VA
No. of patents:
1
Patents:












Patent Number Title Of Patent Date Issued
7557046 Systems and methods for interconnect metallization using a stop-etch layer July 7, 2009
Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method comprises depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a s










 
 
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