Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Veliadis; John V.
Address:
Midlothian, VA
No. of patents:
1
Patents:












Patent Number Title Of Patent Date Issued
7557046 Systems and methods for interconnect metallization using a stop-etch layer July 7, 2009
Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method comprises depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a s










 
 
  Recently Added Patents
Semiconductor assembly and semiconductor package including a solder channel
Method and device for evaluating evolution of tumoural lesions
Method for conductivity control of (Al,In,Ga,B)N
Organic light emitting diode light source device
Switching apparatus and controlling method thereof
Image browsing device, computer control method and information recording medium
Image enhancement based on multiple frames and motion estimation
  Randomly Featured Patents
Optical receiver for computing applications
Turbofan engine assembly and method of assembling same
Pattern recognition template application applied to oil exploration and production
Flat cell and an analyzer using the same
Semiconductor die having sacrificial bond pads for die test
Semiconductor memory device having redundancy circuit portion
Mandibular denture stabilizer
Methods and apparatus for predicting and/or for avoiding lean blow-outs
Cornus plant named `Eva`
Mask-less single electron gun, color crt