Inventor:Veliadis; John V.
No. of patents:1
||Title Of Patent
||Systems and methods for interconnect metallization using a stop-etch layer
||July 7, 2009|
|Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method comprises depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a s|