| Patent Number |
Title Of Patent |
Date Issued |
| 7533223 |
System and method for handling memory requests in a multiprocessor shared memory system |
May 12, 2009 |
| A system and method are provided for tracking memory requests within a data processing system. The system includes a request tracking circuit that is coupled to receive requests for data from multiple processors. Multiple pending requests to the same memory address are tracked using a |
| 7496715 |
Programmable cache management system and method |
February 24, 2009 |
| A memory control system and method is disclosed. The system includes cache tag logic and an optional cache coupled to a main memory. If available, the cache retains a subset of the data stored within the main memory. This subset is selected by programmable control indicators. These i |
| 7299311 |
Apparatus and method for arbitrating for a resource group with programmable weights |
November 20, 2007 |
| A system and method for arbitrating for access to a resource group between agents according to a respective programmable weight for each agent. For each agent, a programmable mapping module selectively couples a respective arbitration handshake signal of the agent to one or more arbi |
| 7260677 |
Programmable system and method for accessing a shared memory |
August 21, 2007 |
| A memory control system and method is disclosed. In one embodiment, a first memory is coupled to one or more additional memories. The first memory receives requests for data that are completed by retrieving the data from the first memory and/or the one or more additional memories. Th |
| 7222222 |
System and method for handling memory requests in a multiprocessor shared memory system |
May 22, 2007 |
| A system and method are provided for tracking memory requests within a data processing system. The system includes a request tracking circuit that is coupled to receive requests for data from multiple processors. Multiple pending requests to the same memory address are tracked using a |
| 7120836 |
System and method for increasing cache hit detection performance |
October 10, 2006 |
| A system and method for increasing computing throughput through execution of parallel data error detection/correction and cache hit detection operations. In one path, hit detection occurs independent of and concurrent with error detection and correction operations, and reliance on hi |
| 7065614 |
System and method for maintaining memory coherency within a multi-processor data processing syst |
June 20, 2006 |
| The current invention provides a system and method for maintaining memory coherency within a multiprocessor environment that includes multiple requesters such as instruction processors coupled to a shared main memory. Within the system of the current invention, data may be provided f |
| 6993630 |
Data pre-fetch system and method for a cache memory |
January 31, 2006 |
| A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines |
| 6973548 |
Data acceleration mechanism for a multiprocessor shared memory system |
December 6, 2005 |
| A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, othe |
| 6973541 |
System and method for initializing memory within a data processing system |
December 6, 2005 |
| An improved system and method are provided for initializing memory in a data processing system. According to one aspect of the invention, a "page zero" instruction is provided that may be executed by an Instruction Processor to initiate memory initialization. Upon instruction execution, |
| 6934810 |
Delayed leaky write system and method for a cache memory |
August 23, 2005 |
| A mechanism to selectively leak data signals from a cache memory is provided. According to one aspect of the invention, an Instruction Processor (IP) is coupled to generate requests to access data signals within the cache. Some requests include a leaky designator, which is activated |
| 6928517 |
Method for avoiding delays during snoop requests |
August 9, 2005 |
| A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from enhancing the response to SNOOP requests. To accomplish this, the system memory bus is provided separate and independent paths t |
| 6857049 |
Method for managing flushes with the cache |
February 15, 2005 |
| A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from managing the process of flushing old data from the second level cache memory. In the present invention, the second level cache |
| 6816952 |
Lock management system and method for use in a data processing system |
November 9, 2004 |
| The current invention provides an improved system and method for locking shared resources. The invention may operate in a data processing environment including a main memory system coupled to multiple instruction processors (IPs). Lock-type instructions are included within the hardware |
| 6799249 |
Split control for IP read and write cache misses |
September 28, 2004 |
| An apparatus for and method of queuing memory access requests resulting from level two cache memory misses. The requests are preferably queued separately by processor. To provide the most recent data to the system, write (i.e., input) requests are optimally given preference over read |
| 6728835 |
Leaky cache mechanism |
April 27, 2004 |
| An apparatus for and method of improving the efficiency of a level two cache memory. In response to a level one cache miss, a request is made to the level two cache. A signal sent with the request identifies when the requester does not anticipate a near term subsequent use for the reques |
| 6697925 |
Use of a cache ownership mechanism to synchronize multiple dayclocks |
February 24, 2004 |
| A method of and apparatus for improving the efficiency of a data processing system employing multiple dayclocks using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from dedicating a separate individual dayclock to each of the mult |
| 6625698 |
Method and apparatus for controlling memory storage locks based on cache line ownership |
September 23, 2003 |
| A system and method for controlling storage locks based on cache line ownership. Ownership of target data segments is acquired at a memory targeted by a first requesting device. A storage lock is enabled that prohibits requesting devices, other than the first requesting device, from |
| 6374332 |
Cache control system for performing multiple outstanding ownership requests |
April 16, 2002 |
| An improved directory-based, hierarchical memory system is disclosed that is capable of simultaneously processing multiple ownership requests initiated by a processor that is coupled to the memory. An ownership request is initiated on behalf of a processor to obtain an exclusive copy |
| 5678026 |
Multi-processor data processing system with control for granting multiple storage locks in paral |
October 14, 1997 |
| A storage lock apparatus for a multiprocessor data processing system. The storage lock apparatus includes control for granting locks to different selectable portions of storage in parallel. In addition, acknowledgment from a remote lock controller is not required for a processor to obtai |
