| Patent Number |
Title Of Patent |
Date Issued |
| 7474716 |
Data recovery circuits using oversampling for maverick edge detection/suppression |
January 6, 2009 |
| A data recovery circuit employing an oversampling technique. The incoming serial data stream with jitter is oversampled by means of the multiple phases of a reference clock to produce data samples. Each sample is compared to the samples collected with the next clock phase in an edge |
| 7406142 |
Data recovery circuits using oversampling for best data sample selection |
July 29, 2008 |
| An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or transitions). The incoming serial data stream with jitter is oversampled in an oversampling circuit |
| 7251764 |
Serializer/deserializer circuit for jitter sensitivity characterization |
July 31, 2007 |
| Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is |
| 7180966 |
Transition detection, validation and memorization circuit |
February 20, 2007 |
| A transition detection, validation and memorization (TDVM) circuit detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best data. The incoming d |
| 7142621 |
Method and circuit for recovering a data signal from a stream of binary data |
November 28, 2006 |
| There is disclosed a data recovery (DR) circuit including an over sampling (OS) circuit, a transition detection (TD) circuit and a sample selection/data alignment (SSDA) circuit. A multiphase clock generating circuit delivering n phases is coupled to each of these circuits. The OS ci |
| 7136443 |
Sample selection and data alignment circuit |
November 14, 2006 |
| There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G.sub.0, . . . , G.sub.n-1) is obtained by over sampling an incoming serial binary data (b |
| 6834367 |
Built-in self test system and method for high speed clock and data recovery circuit |
December 21, 2004 |
| A built-in self test system for testing a clock and data recovery circuit. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing mean |
| 6111471 |
Apparatus and method for setting VCO free-running frequency |
August 29, 2000 |
| The present invention provides an apparatus for setting the free-running frequency of a VCO to a reference frequency. The apparatus comprises frequency range means for setting the VCO within a VCO frequency range among a plurality of VCO frequency ranges. First counting means are ope |
| 5112765 |
Method of forming stacked tungsten gate PFET devices and structures resulting therefrom |
May 12, 1992 |
| A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysil |
