| Patent Number |
Title Of Patent |
Date Issued |
| 7555084 |
System and method of digital system performance enhancement |
June 30, 2009 |
| The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical |
| 7409534 |
Automatic and transparent hardware conversion of traditional control flow to predicates |
August 5, 2008 |
| A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the |
| 7380108 |
Automatic and transparent hardware conversion of traditional control flow to predicates |
May 27, 2008 |
| A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the |
| 7210025 |
Automatic and transparent hardware conversion of traditional control flow to predicates |
April 24, 2007 |
| A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the |
| 6985547 |
System and method of digital system performance enhancement |
January 10, 2006 |
| The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical |
| 6976150 |
Resource flow computing device |
December 13, 2005 |
| A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The |
| 5201057 |
System for extracting low level concurrency from serial instruction streams |
April 6, 1993 |
| An architecture for a central processing unit (cpu) provides for the extraction of low-level concurrency from sequential instruction streams. The cpu includes an instruction queue, a plurality of processing elements, a sink storage matrix for temporary storage of data elements, and r |
