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Inventor: Ueda; Yutaka
Address: Kawasaki, JP
No. of patents: 1
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 6876568 |
Timing adjusting circuit and semiconductor memory device |
April 5, 2005 |
| In a memory cell array, a plurality of memory cells having ferroelectric capacitors are arranged. A plurality of sense amplifier circuits amplifies the potential of the bit line of each memory cell. A column decoder outputs activation signals to activate the sense amplifier circuits. |
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