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Inventor:
Turner; John
Address:
Santa Cruz, CA
No. of patents:
16
Patents:












Patent Number Title Of Patent Date Issued
7684532 Clock data recovery circuitry associated with programmable logic device circuitry March 23, 2010
A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate
7602634 Dynamic RAM storage techniques October 13, 2009
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell
7465971 Integrated circuit structures for increasing resistance to single event upset December 16, 2008
A configuration memory cell ("CRAM") for a field programmable gate array ("FPGA") integrated circuit ("IC") device is given increased resistance to single event upset ("SEU"). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size
7333570 Clock data recovery circuitry associated with programmable logic device circuitry February 19, 2008
A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate
7298646 Apparatus for configuring programmable logic devices and associated methods November 20, 2007
A programmable logic device (PLD) includes a non-volatile configuration memory. The non-volatile configuration memory is adapted to configure programmable resources (such as programmable logic and programmable interconnect) within the PLD. The non-volatile configuration memory may co
7277316 Dynamic RAM storage techniques October 2, 2007
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell
7227918 Clock data recovery circuitry associated with programmable logic device circuitry June 5, 2007
A programmable logic device ("PLD") is augmented with programmable clock data recover ("CDR") circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate
7088606 Dynamic RAM storage techniques August 8, 2006
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell
6952114 Apparatus and methods for silicon-on-insulator transistors in programmable logic devices October 4, 2005
A programmable logic device (PLD) includes programmable electronic circuitry. The programmable electronic circuitry allows programming the functionality of the PLD. The programmable electronic circuitry includes one or more of programmable interconnects, pass devices, look-up table c
6781409 Apparatus and methods for silicon-on-insulator transistors in programmable logic devices August 24, 2004
A programmable logic device (PLD) includes programmable electronic circuitry. The programmable electronic circuitry allows programming the functionality of the PLD. The programmable electronic circuitry includes one or more of programmable interconnects, pass devices, look-up table c
6629311 Apparatus and method for configuring a programmable logic device with a configuration controller September 30, 2003
An apparatus to configure a programmable logic device includes a configuration memory to store configuration data. A configuration controller retrieves the configuration data, converts the configuration data to re-fomatted configuration data, and passes the re-formatted configuration
6335635 Programmable reticle stitching January 1, 2002
Design methodologies and techniques for significantly increasing logic density by stitching multiple reticles together are disclosed. The invention teaches various techniques to ensure continuity of interconnections and sealing mechanisms across the stitch region. The stitch extended
6269020 FIFO configuration cell July 31, 2001
A memory cell and a method of writing to a memory cell where a switch couples the output of a latch cell to a predetermined potential in response to a data signal and a control signal is disclosed. In one embodiment the switch includes two transistors, wherein the first transistor is
6255850 Integrated circuit with both clamp protection and high impedance protection from input overshoot July 3, 2001
An integrated circuit is provided for use with a supply voltage and which includes an input/output (I/O) circuit with an output driver with a pull-up transistor and a pull-down transistor and which includes an I/O pin connected to receive output signals from the output driver and con
6150840 Programmable reticle stitching November 21, 2000
Design methodologies and techniques for significantly increasing logic density by stitching multiple reticles together are disclosed. The invention teaches various techniques to ensure continuity of interconnections and sealing mechanisms across the stitch region. The stitch extended
5945870 Voltage ramp rate control circuit August 31, 1999
Various embodiments for controlling a ramp rate of a high voltage generator circuit such as a charge pump circuit are disclosed. In one embodiment the ramp rate of the output signal is controlled by modulating an amplitude of the oscillating signal at the input of the charge pump circuit










 
 
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