| Patent Number |
Title Of Patent |
Date Issued |
| 7557399 |
Metal-insulator-metal capacitors |
July 7, 2009 |
| A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or sili |
| 7382012 |
Reducing parasitic capacitance of MIM capacitor in integrated circuits by reducing effective die |
June 3, 2008 |
| A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectri |
| 7381613 |
Self-aligned MIM capacitor process for embedded DRAM |
June 3, 2008 |
| A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive material layers. The first |
| 7355240 |
Semiconductor product including logic, non-volatile memory and volatile memory devices and metho |
April 8, 2008 |
| A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device formed therein and a |
| 7329953 |
Structure for reducing leakage currents and high contact resistance for embedded memory and meth |
February 12, 2008 |
| A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched in the planar ins |
| 7282757 |
MIM capacitor structure and method of manufacture |
October 16, 2007 |
| A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor device. A top portion o |
| 7271083 |
One-transistor random access memory technology compatible with metal gate process |
September 18, 2007 |
| One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a cap |
| 7262090 |
Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolat |
August 28, 2007 |
| A process for fabricating a novel random access memory (RAM) capacitor in a shallow trench isolation (STI) The method utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel photoresist mask |
| 7199423 |
Non-volatile memory technology compatible with 1T-RAM process |
April 3, 2007 |
| Methods of fabricating memory devices having non-volatile and volatile memory are provided. A substrate is provided, wherein the substrate has a non-volatile memory region and a volatile memory region. The non-volatile memory region has a storage device, such as a split-gate transistor, |
| 7195970 |
Metal-insulator-metal capacitors |
March 27, 2007 |
| A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or sili |
| 7189613 |
Method and structure for metal-insulator-metal capacitor based memory device |
March 13, 2007 |
| A process for integrally fabricating a memory cell capacitor and a logic device is disclosed. A first conductive layer and second conductive layer are formed above a semiconductor substrate with a logic region and memory cell region. A first photoresist layer is formed to cover the logic |
| 7163853 |
Method of manufacturing a capacitor and a metal gate on a semiconductor device |
January 16, 2007 |
| A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom electrode layer in the |
| 7115935 |
Embedded DRAM for metal-insulator-metal (MIM) capacitor structure |
October 3, 2006 |
| A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the sub |
| 7071509 |
Method of improving the top plate electrode stress inducting voids for 1T-RAM process |
July 4, 2006 |
| A method for fabricating a capacitor with overlying transistor without stress-induced voids is described. A capacitor stack is provided overlying a substrate. A stress-balancing dielectric layer is deposited overlying the stack. An anti-reflective coating (ARC) layer is deposited ove |
| 7030444 |
Space process to prevent the reverse tunneling in split gate flash |
April 18, 2006 |
| A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and |
| 7029968 |
Method of forming a PIP capacitor |
April 18, 2006 |
| A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor in a mixed mode semiconductor device. A floating gate of a split gate transistor and a bottom electrode of a PIP capacitor are formed from a first polysilicon layer using a single lithography mask. Poly-oxide reg |
| 7019348 |
Embedded semiconductor product with dual depth isolation regions |
March 28, 2006 |
| An embedded semiconductor product employs a first isolation trench and first isolation region formed therein adjoining a logic cell active region of a semiconductor substrate. The embedded semiconductor product also employs a second isolation trench and second isolation region formed |
| 6949785 |
Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolat |
September 27, 2005 |
| A process for fabricating a novel random access memory (RAM) capacitor in a shallow trench isolation (STI). The method utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel photoresist mask |
| 6902975 |
Non-volatile memory technology compatible with 1T-RAM process |
June 7, 2005 |
| Methods of fabricating memory devices having non-volatile and volatile memory are provided. A substrate is provided, wherein the substrate has a non-volatile memory region and a volatile memory region. The non-volatile memory region has a storage device, such as a split-gate transistor, |
| 6872622 |
Method of forming a capacitor top plate structure to increase capacitance and to improve top pla |
March 29, 2005 |
| A process for fabricating a capacitor under bit line (CUB), DRAM device, featuring increased capacitor storage node surface area, and increased overlay margin between storage node and bit line structures, has been developed. The process features the definition of hemispherical grain |
| 6867129 |
Method of improving the top plate electrode stress inducting voids for 1T-RAM process |
March 15, 2005 |
| A method for fabricating a capacitor with overlying transistor without stress-induced voids is described. A capacitor stack is provided overlying a substrate. A stress-balancing dielectric layer is deposited overlying the stack. An anti-reflective coating (ARC) layer is deposited overlyi |
| 6853024 |
Self-aligned MIM capacitor process for embedded DRAM |
February 8, 2005 |
| A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive material layers. The first |
| 6833578 |
Method and structure improving isolation between memory cell passing gate and capacitor |
December 21, 2004 |
| A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electr |
| 6812093 |
Method for fabricating memory cell structure employing contiguous gate and capacitor dielectric |
November 2, 2004 |
| A method for fabricating a memory cell structure provides for fabricating a capacitor within the memory cell structure within an asymmetric trench within an isolation region adjoining an active region such that a capacitor node layer within the capacitor contacts a sidewall of the ac |
| 6764967 |
Method for forming low thermal budget sacrificial oxides |
July 20, 2004 |
| A method for forming a silicon dioxide layer over a silicon substrate including providing a substrate having exposed silicon portions; and, forming a silicon dioxide layer over the exposed silicon portions according to an oxide formation process including contacting the exposed silic |
| 6734526 |
Oxidation resistant microelectronics capacitor structure with L shaped isolation spacer |
May 11, 2004 |
| A capacitor structure within a microelectronic product employs at least one of: (1) an oxidation barrier layer formed upon a second capacitor plate within the capacitor structure; and (2) a spacer formed adjoining a sidewall of the second capacitor plate, where the spacer is formed with |
| 6720232 |
Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure |
April 13, 2004 |
| A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the sub |
| 6709919 |
Method for making auto-self-aligned top electrodes for DRAM capacitors with improved capacitor-t |
March 23, 2004 |
| Novel capacitor top electrodes auto-self-aligned to bit-line regions is achieved with improved process yields. A first insulating layer is formed over the FETs, and a second insulating layer is deposited. Openings are etched for capacitors, and a novel photomask and etching are used to |
| 6682982 |
Process method for 1T-SRAM |
January 27, 2004 |
| A method of forming a cell memory structure including the step of planarizing an HDP/LDP oxide layer lying over a capacitor area. The method provides for the planarization of the cell storage node, good isolation between the transistor and storage node, reduced step height for the ce |
| 6642097 |
Structure for capacitor-top-plate to bit-line-contact overlay margin |
November 4, 2003 |
| A novel method and structure are described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After insulating the FETs with a first insulating layer, a second insulating layer is deposited and first open |
| 6627493 |
Self-aligned method for fabricating a capacitor under bit-line (cub) dynamic random access memor |
September 30, 2003 |
| Within a method for fabricating a dynamic random access memory (DRAM) cell structure there is first anisotropically sequentially etched a blanket hard mask layer and a blanket capacitor plate layer which both cover a bit-line source/drain region within the dynamic random access memory |
| 6602749 |
Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance |
August 5, 2003 |
| Within a method for forming a memory cell structure there is provided a field effect transistor (FET) device having electrically connected to one of its source/drain regions a storage capacitor and electrically connected to the other of its source/drain regions a bitline stud layer separ |
| 6503796 |
Method and structure for a top plate design for making capacitor-top-plate to bit-line-contact o |
January 7, 2003 |
| A novel method and structure are described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After insulating the FETs with a first insulating layer, a second insulating layer is deposited and first open |
| 6486033 |
SAC method for embedded DRAM devices |
November 26, 2002 |
| A method for forming logic circuits with embedded memory is described. Isolation areas are formed on a semiconductor substrate separating at least one logic area and at least one memory area. Gate electrode stacks comprising a polysilicon layer, a silicide layer, a first oxide layer, and |
| 6300191 |
Method of fabricating a capacitor under bit line structure for a dynamic random access memory de |
October 9, 2001 |
| A process of forming a capacitor under bit line (CUB), structure, for a DRAM device, highlighted by simultaneous definition of the storage node structures, and a bit line contact structure, and by simultaneous definition of the capacitor top plate, and the bit line opening, has been |
| 6294426 |
Method of fabricating a capacitor under bit line structure with increased capacitance without in |
September 25, 2001 |
| A process for fabricating a capacitor under bit line (CUM), DRAM device, featuring increased capacitance, without increasing the aspect ratio for a dry etched, narrow diameter bit line contact hole, has been developed. The process features increasing the vertical space in a capacitor ope |
| 6200898 |
Global planarization process for high step DRAM devices via use of HF vapor etching |
March 13, 2001 |
| A process to obtain a level top surface topography, for a semiconductor chip comprised with high step height, DRAM crown shaped capacitor structures, as well as comprised with lower step height, peripheral logic devices, has been developed. The process features the use of selective v |
