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Tsuto; Masaru
Saitama, JP
No. of patents:

Patent Number Title Of Patent Date Issued
8165027 Test apparatus and test method April 24, 2012
There is provided a test apparatus for testing at least one device under test, including a packet list storing section that stores a plurality of packet lists each of which includes a series of packets communicated between the test apparatus and the at least one device under test, a flow
8149721 Test apparatus and test method April 3, 2012
There is provided a test apparatus for testing a device under test, including an obtaining section that obtains a packet sequence communicated between the test apparatus and the device under test, from a simulation environment for simulating an operation of the device under test, a p
8059547 Test apparatus and test method November 15, 2011
Provided is a test apparatus that tests a device under test, comprising an upper sequencer that sequentially designates packets transmitted to and from the device under test, by executing a test program for testing the device under test; a packet data sequence storing section that stores
6138259 Semiconductor memory testing apparatus October 24, 2000
In a semiconductor memory testing apparatus for testing a DRAM which requires a refresh operation, plural pattern generation parts are operated normally to generate high-speed pattern signals. The plural pattern generation parts are connected to a common sequence control part and con
5850402 Test pattern generator December 15, 1998
It is to provide a test pattern generator that can easily generate expected value data for arbitrary initial values when testing a memory device having a function of write enable/disable control per bit. The pattern generator includes an XOR controller (131) which generates a control

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