| Patent Number |
Title Of Patent |
Date Issued |
| 7511349 |
Contact or via hole structure with enlarged bottom critical dimension |
March 31, 2009 |
| An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the b |
| 7265060 |
Bi-level resist structure and fabrication method for contact holes on semiconductor substrates |
September 4, 2007 |
| An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique comb |
| 7265056 |
Method for forming novel BARC open for precision critical dimension control |
September 4, 2007 |
| A method for forming an opening in a semiconductor device is provided. In one embodiment, a bottom anti-reflective coating (BARC) layer is formed overlying an insulation layer of a substrate. A patterned photoresist layer including at least one opening therein is formed overlying the BAR |
| 7256137 |
Method of forming contact plug on silicide structure |
August 14, 2007 |
| A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer |
| 7223647 |
Method for forming integrated advanced semiconductor device using sacrificial stress layer |
May 29, 2007 |
| An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS |
| 7078351 |
Photoresist intensive patterning and processing |
July 18, 2006 |
| A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask |
| 7067235 |
Bi-layer photoresist dry development and reactive ion etch method |
June 27, 2006 |
| A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure |
| 6884736 |
Method of forming contact plug on silicide structure |
April 26, 2005 |
| A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop l |
| 6878639 |
Borderless interconnection process |
April 12, 2005 |
| A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer m |
| 6867084 |
Gate structure and method of forming the gate dielectric with mini-spacer |
March 15, 2005 |
| A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/dra |
| 6838381 |
Methods for improving sheet resistance of silicide layer after removal of etch stop layer |
January 4, 2005 |
| A method of manufacturing a semiconductor device is provided. A nickel silicide layer (e.g., NiSi) is formed on a substrate. Next, a hydrogen plasma treatment may be performed on the silicide layer, which may induce the formation of metal/silicon hydride bonds in the silicide layer. An |
| 6828205 |
Method using wet etching to trim a critical dimension |
December 7, 2004 |
| A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of |
| 6780782 |
Bi-level resist structure and fabrication method for contact holes on semiconductor substrates |
August 24, 2004 |
| An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique comb |
| 6706640 |
Metal silicide etch resistant plasma etch method |
March 16, 2004 |
| A plasma etch method for etching a dielectric layer and an etch stop layer to reach a metal silicide layer formed thereunder employs for etching the etch stop layer an etchant gas composition comprising a fluorine containing gas and a nitrogen containing gas, preferably with a carrier |
| 6407002 |
Partial resist free approach in contact etch to improve W-filling |
June 18, 2002 |
| A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening--which can be used either as a contact or via hole--with a faceted entrance along with tapered side-walls. This combination of faceted e |
| 6399437 |
Enhanced side-wall stacked capacitor |
June 4, 2002 |
| A method of forming a stacked capacitor having improved capacitance in a dynamic random access memory device is provided wherein and additional pad polysilicon layer is deposited prior to the forming of the capacitor cell contact area such that the side-wall of the capacitor cell can be |
| 5824234 |
Method for forming low contact resistance bonding pad |
October 20, 1998 |
| The present invention provides a method for forming a bonding pad having a low contact resistance. The method includes steps of: a) forming a bonding pad structure on a substrate having a metal layer by forming a passivation layer over said metal layer and etching the passivation layer w |
