| Patent Number |
Title Of Patent |
Date Issued |
| 7372102 |
Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology |
May 13, 2008 |
| A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided. |
| 7250344 |
Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology |
July 31, 2007 |
| A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided. |
| 7015086 |
Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology |
March 21, 2006 |
| A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features |
| 6747336 |
Twin current bipolar device with hi-lo base profile |
June 8, 2004 |
| A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to |
| 6569730 |
High voltage transistor using P+ buried layer |
May 27, 2003 |
| A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown vol |
| 6423590 |
High voltage transistor using P+ buried layer |
July 23, 2002 |
| A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown vol |
| 6396126 |
High voltage transistor using P+ buried layer |
May 28, 2002 |
| A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown vol |
| 6340833 |
Integrated circuit polysilicon resistor having a silicide extension to achieve 100 % metal shiel |
January 22, 2002 |
| A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide i |
| 6245609 |
High voltage transistor using P+ buried layer |
June 12, 2001 |
| A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown vol |
| 6242313 |
Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage |
June 5, 2001 |
| A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates,. placed on field oxide regions, |
| 6211028 |
Twin current bipolar device with hi-lo base profile |
April 3, 2001 |
| A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to |
| 6165861 |
Integrated circuit polysilicon resistor having a silicide extension to achieve 100% metal shield |
December 26, 2000 |
| A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide i |
| 6162695 |
Field ring to improve the breakdown voltage for a high voltage bipolar device |
December 19, 2000 |
| A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of field ring regions, placed in an N well region, and locat |
| 6096629 |
Uniform sidewall profile etch method for forming low contact leakage schottky diode contact |
August 1, 2000 |
| A method for forming a Schottky diode. There is first provided a silicon layer. There is then formed upon the silicon layer an anisotropically patterned first dielectric layer which defines a Schottky diode contact region of the silicon layer. There is then formed and aligned upon the |
