| Patent Number |
Title Of Patent |
Date Issued |
| 7561465 |
Methods and systems for recovering data in a nonvolatile memory array |
July 14, 2009 |
| One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage win |
| 7465956 |
Stacked organic memory devices and methods of operating and fabricating |
December 16, 2008 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 7391064 |
Memory device with a selection element and a control line in a substantially similar layer |
June 24, 2008 |
| The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wo |
| 7361586 |
Preamorphization to minimize void formation |
April 22, 2008 |
| Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diff |
| 7232765 |
Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias |
June 19, 2007 |
| Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE copper plugs) and non |
| 7220642 |
Protection of active layers of memory cells during processing of other elements |
May 22, 2007 |
| A method of fabricating an electronic structure by providing a conductive layer, providing a dielectric layer over the conductive layer, providing first and second openings through the dielectric layer, providing first and second conductive bodies in the first and second openings res |
| 7199416 |
Systems and methods for a memory and/or selection element formed within a recess in a metal line |
April 3, 2007 |
| The subject invention provides systems and methodologies for fabrication of memory and/or selection (e.g., diodes) elements in a recession in a semiconductor layer. In particular, a trench of varying width is created in the semiconductor layer by employing various etching techniques. A |
| 7035141 |
Diode array architecture for addressing nanoscale resistive memory arrays |
April 25, 2006 |
| The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memor |
| 7001807 |
Fully isolated dielectric memory cell structure for a dual bit nitride storage device and proces |
February 21, 2006 |
| A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a ga |
| 6979837 |
Stacked organic memory devices and methods of operating and fabricating |
December 27, 2005 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 6977389 |
Planar polymer memory device |
December 20, 2005 |
| The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and |
| 6872643 |
Implant damage removal by laser thermal annealing |
March 29, 2005 |
| A method of manufacturing a semiconductor device includes forming a layer over a substrate, and doping the layer with a dopant, after which the layer is laser thermal annealed. The layer can be a nitride, an oxide, or a polysilicon layer. The dopants can be arsenic, phosphorous, boron, o |
| 6870183 |
Stacked organic memory devices and methods of operating and fabricating |
March 22, 2005 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 6861307 |
Fully isolated dielectric memory cell structure for a dual bit nitride storage device and proces |
March 1, 2005 |
| A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate |
| 6852586 |
Self assembly of conducting polymer for formation of polymer memory cell |
February 8, 2005 |
| The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer self assembles relative to a conductive electrode. The process affords self-assembly such that |
| 6803272 |
Use of high-K dielectric material in modified ONO structure for semiconductor devices |
October 12, 2004 |
| A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6783591 |
Laser thermal annealing method for high dielectric constant gate oxide films |
August 31, 2004 |
| A method of manufacturing a semiconductor device, including depositing a gate oxide film over a substrate and conditioning the deposited gate oxide film using laser thermal annealing in a single process chamber, and depositing a gate electrode film over the conditioned gate oxide film. |
| 6753570 |
Memory device and method of making |
June 22, 2004 |
| A non-volatile memory device includes insulators between floating gates. The insulators each include both a lower trench-fill insulator portion in a trench in the substrate, and an upper protruding portion that protrudes from the substrate. Floating gates extend between the protruding po |
| 6753247 |
Method(s) facilitating formation of memory cell(s) and patterned conductive |
June 22, 2004 |
| A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is appl |
| 6746971 |
Method of forming copper sulfide for memory cell |
June 8, 2004 |
| An organic memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The controllably conductive media changes its impedance when an ext |
| 6735123 |
High density dual bit flash memory cell with non planar structure |
May 11, 2004 |
| A dual bit dielectric memory cell comprises a substrate with a source region and a drain region implanted on opposing sides of a central channel region. A multilevel charge trapping dielectric is positioned on the substrate above the central channel region and includes a central region |
| 6674138 |
Use of high-k dielectric materials in modified ONO structure for semiconductor devices |
January 6, 2004 |
| A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric mater |
| 6667243 |
Etch damage repair with thermal annealing |
December 23, 2003 |
| A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist |
| 6639271 |
Fully isolated dielectric memory cell structure for a dual bit nitride storage device and proces |
October 28, 2003 |
| A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate |
| 6630383 |
Bi-layer floating gate for improved work function between floating gate and a high-K dielectric |
October 7, 2003 |
| In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer an |
| 6627945 |
Memory device and method of making |
September 30, 2003 |
| A non-volatile memory device includes a number of memory cells, parts of which are delineated by insulators. The insulators each include both a lower trench-fill insulator portion in a trench in the substrate, and an upper protruding portion that protrudes from the substrate. Between eac |
| 6579778 |
Source bus formation for a flash memory using silicide |
June 17, 2003 |
| A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating ga |
| 6548855 |
Non-volatile memory dielectric as charge pump dielectric |
April 15, 2003 |
| A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric |
| 6500713 |
Method for repairing damage to charge trapping dielectric layer from bit line implantation |
December 31, 2002 |
| A method of forming a buried bit in line in MONOS cell implants dopant into a substrate through a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer. The implantation process damages the ONO layer. A laser thermal annealing process repairs the damage to the ONO |
| 6455888 |
Memory cell structure for elimination of oxynitride (ONO) etch residue and polysilicon stringers |
September 24, 2002 |
| A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. A |
| 6420702 |
Non-charging critical dimension SEM metrology standard |
July 16, 2002 |
| An SEM measurement standard for measuring linewidths of 0.1 microns and below utilizes two different conducting materials in order to prevent charging effects. The top material is selected to use grain morphology to focus secondary electrons, and to obtain improved image contrast. The |
| 6410956 |
Method and system for using a spacer to offset implant damage and reduce lateral diffusion in fl |
June 25, 2002 |
| A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at lea |
| 6355933 |
Ion source and method for using same |
March 12, 2002 |
| Damaging forming deposits and etching is reduced in an ion source by introducing an oxygenated gas during operation of the ion source. Embodiments include an ion source in fluid communication with a source of oxygenated gas and introducing about 1% to about 10% of carbondioxide as th |
| 6153487 |
Approach for the formation of semiconductor devices which reduces band-to-band tunneling current |
November 28, 2000 |
| The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the |
| 6110833 |
Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floa |
August 29, 2000 |
| A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. A |
| 6063665 |
Method for silicon surface control for shallow junction formation |
May 16, 2000 |
| A system and method for providing a small device formed on a semiconductor is disclosed. The method and system include controlling the surface by providing a very thin oxide layer and providing a shallow implant through the very thin oxide layer. |
| 6043120 |
Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floa |
March 28, 2000 |
| A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer i |
| 6034395 |
Semiconductor device having a reduced height floating gate |
March 7, 2000 |
| Arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The arrangements effectively reduce the severity of the topology attributable to the space between adjacent float |
| 6030868 |
Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floa |
February 29, 2000 |
| A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first a |
| 6025240 |
Method and system for using a spacer to offset implant damage and reduce lateral diffusion in fl |
February 15, 2000 |
| A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at lea |
| 5888867 |
Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration |
March 30, 1999 |
| Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-ge |
| 5866467 |
Method of improving oxide isolation in a semiconductor device |
February 2, 1999 |
| A silicon substrate has patterned thereon a pad oxide layer and a nitride layer. The exposed surface of the silicon substrate is cleaned of residual oxide, and a layer of oxidizable material such as polysilicon is deposit over the resulting structure. The polysilicon layer is anisotropic |
| 5789802 |
Dopant profile spreading for arsenic source/drain |
August 4, 1998 |
| An improved process for forming shallow arsenic-doped source/drain regions in MOS devices utilizes a two-step arsenic implant which lowers the surface arsenic concentration while maintaining sharp junction profile and desired junction depth. Minimizing the excess arsenic in the surface |
