| Patent Number |
Title Of Patent |
Date Issued |
| 7319341 |
Method of maintaining signal integrity across a capacitive coupled solder bump |
January 15, 2008 |
| The present invention is a novel method and computer program product which utilizes an interface capacitor formed by the metal of the probe tip, a dielectric layer, such as an oxide, formed by a contaminant on a solder bump and the metal of the solder bump. The interface capacitor forms |
| 7237106 |
System for loading configuration data into a configuration word register by independently loadin |
June 26, 2007 |
| A programmable device with an improved system for loading configuration data compresses configuration data by composing configuration data out of pairs of control words and data words. The configuration data is divided into configuration words. Each configuration word is further divided |
| 7103813 |
Method and apparatus for testing interconnect bridging faults in an FPGA |
September 5, 2006 |
| A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adapta |
| 7058534 |
Method and apparatus for application specific test of PLDs |
June 6, 2006 |
| Method and apparatus for application specific testing of PLDs. The PLD has a number of resources, less than all of which are used for implementing a customer application. The method includes the following steps. The set of resources that is used for implementing the customer application |
| 7005875 |
Built-in self-test circuitry for integrated circuits |
February 28, 2006 |
| Circuits, methods, and apparatus for output response analyzers that may be used during integrated circuit testing. Current output test data is compared with previous output test data. In this way, repetitive test patterns such as checkerboards may be employed while limiting circuit c |
