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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Tokunaga; Takafumi
Address:
Iruma, JP
No. of patents:
20
Patents:












Patent Number Title Of Patent Date Issued
7737023 Method of manufacture of semiconductor integrated circuit device and semiconductor integrated ci June 15, 2010
In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes
7427537 Semiconductor integrated circuit device and method for manufacturing the same September 23, 2008
In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM,
7419902 Method of manufacture of semiconductor integrated circuit September 2, 2008
In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes
7259104 Sample surface processing method August 21, 2007
A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample
7118949 Semiconductor integrated circuit device and method for manufacturing the same October 10, 2006
In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM,
7049243 Surface processing method of a specimen and surface processing apparatus of the specimen May 23, 2006
A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the
6849191 Method and apparatus for treating surface of semiconductor February 1, 2005
According to the present invention, there is provided a sample surface treating apparatus for processing a fine pattern by plasma etching, including a stage provided in a chamber, on which a sample to be subjected to a surface treatment is placed; etching gas supply source for contin
6838320 Method for manufacturing a semiconductor integrated circuit device January 4, 2005
In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM,
6791137 Semiconductor integrated circuit device and process for manufacturing the same September 14, 2004
In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of t
6767838 Method and apparatus for treating surface of semiconductor July 27, 2004
A method and apparatus of treating a surface of a sample. A sample is arranged on a stage provided in a chamber, an etching gas is continuously supplied into the chamber and a plasma is generated from the etching gas. An rf bias at a frequency of 100 kHz or higher is applied to the stage
6677244 Specimen surface processing method January 13, 2004
A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage
6660647 Method for processing surface of sample December 9, 2003
A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a
6555861 Semiconductor integrated circuit device and process for manufacturing the same April 29, 2003
In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of t
6492277 Specimen surface processing method and apparatus December 10, 2002
Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the brea
6309980 Semiconductor integrated circuit arrangement fabrication method October 30, 2001
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta
6191045 Method of treating surface of sample February 20, 2001
In order to provide a method of treating a multilayer including metal and polysilicon for use in a conductor or a gate electrode of a semiconductor device with high accuracy at a high selectivity, the temperature of a sample is maintained at 100.degree. C. or higher at the time of etchin
6074958 Semiconductor integrated circuit arrangement fabrication method June 13, 2000
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta
5962347 Semiconductor integrated circuit arrangement fabrication method October 5, 1999
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta
5933726 Method of forming a semiconductor device have a screen stacked cell capacitor August 3, 1999
A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode
5874013 Semiconductor integrated circuit arrangement fabrication method February 23, 1999
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta










 
 
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