| Patent Number |
Title Of Patent |
Date Issued |
| 7555634 |
Multiple data hazards detection and resolution unit |
June 30, 2009 |
| Order indication logic can be recycled for at least two different data hazards, thus reducing the amount of processor real estate consumed by data hazard resolution logic. The logic also allows a single priority picker to be utilized for coloring without the cost of additional pipeli |
| 7020752 |
Apparatus and method for snoop access in a dual access, banked and pipelined data cache memory u |
March 28, 2006 |
| In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. The data cache unit has a plurality of storage cell banks. Eac |
| 6973557 |
Apparatus and method for dual access to a banked and pipelined data cache memory unit |
December 6, 2005 |
| In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. For a READ operation, virtual address components are applied t |
| 6073212 |
Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags |
June 6, 2000 |
| An apparatus and method for optimizing a non-inclusive hierarchical cache memory system that includes a first and second cache for storing information. The first and second cache are arranged in an hierarchical manner such as a level two and level three cache in a cache system having thr |
| 5909697 |
Reducing cache misses by snarfing writebacks in non-inclusive memory systems |
June 1, 1999 |
| A non-inclusive multi-level cache memory system is optimized by removing a first cache content from a first cache, so as to provide cache space in the first cache. In response to a cache miss in the first and second caches, the removed first cache content is stored in a second cache. All |
