| Patent Number |
Title Of Patent |
Date Issued |
| RE36050 |
Method for repeatable temperature measurement using surface reflectivity |
January 19, 1999 |
| A method is disclosed for continuously measuring the temperature of a semiconductor substrate in a chamber is disclosed. The first step of the method involves providing a substantially clean semiconductor substrate having a layer a reflective surface thereon into a chamber. A film is |
| 7485961 |
Approach to avoid buckling in BPSG by using an intermediate barrier layer |
February 3, 2009 |
| A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed |
| 7432152 |
Methods of forming HSG layers and devices |
October 7, 2008 |
| A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using |
| 7235498 |
Process for growing a dielectric layer on a silicon-containing surface using a mixture of N.sub. |
June 26, 2007 |
| This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N.sub.2O) and ozone (O.sub.3). The presence of O.sub.3 in the oxidizing ambiance greatly enhances the oxidation rate compar |
| 7232728 |
High quality oxide on an epitaxial layer |
June 19, 2007 |
| This invention improves the quality of gate oxide dielectric layers using a two-pronged approach, thus permitting the use of much thinner silicon dioxide gate dielectric layers required for lower-voltage, ultra-dense integrated circuits. In order to eliminate defects caused by imperf |
| 7229890 |
Forming integrated circuits using selective deposition of undoped silicon film seeded in chlorin |
June 12, 2007 |
| A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using |
| 7192889 |
Methods for forming a high dielectric film |
March 20, 2007 |
| A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 |
| 7067442 |
Method to avoid threshold voltage shift in thicker dielectric films |
June 27, 2006 |
| A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region |
| 7067411 |
Method to prevent metal oxide formation during polycide reoxidation |
June 27, 2006 |
| A selective spacer to prevent metal oxide formation during polycide reoxidation of a feature such as an electrode and a method for forming the selective spacer are disclosed. A material such as a thin silicon nitride or an amorphous silicon film is selectively deposited on the electr |
| 7009264 |
Selective spacer to prevent metal oxide formation during polycide reoxidation |
March 7, 2006 |
| A selective spacer to prevent metal oxide formation during polycide reoxidation of a feature such as an electrode and a method for forming the selective spacer are disclosed. A material such as a thin silicon nitride or an amorphous silicon film is selectively deposited on the electr |
| 6974773 |
High pressure anneals of integrated circuit structures |
December 13, 2005 |
| According to one embodiment of the invention, a high pressure anneal is utilized to form titanium silicide at the bottom of a contact hole, at a pressure of at least approximately 1.1 atmospheres, from a reaction between deposited titanium and underlying silicon. When such high press |
| 6927179 |
Methods and apparatus for forming a high dielectric film and the dielectric film formed thereby |
August 9, 2005 |
| A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 |
| 6887774 |
Conductor layer nitridation |
May 3, 2005 |
| Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin n |
| 6864561 |
Method and apparatus for reducing fixed charge in semiconductor device layers |
March 8, 2005 |
| The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O.sub.3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to |
| 6864125 |
Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O an |
March 8, 2005 |
| This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N.sub.2 O) and ozone (O.sub.3). The presence of O.sub.3 in the oxidizing ambiance greatly enhances the oxidation rate compa |
| 6798026 |
Conductor layer nitridation |
September 28, 2004 |
| Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin n |
| 6794703 |
High pressure reoxidation/anneal of high dielectric constant |
September 21, 2004 |
| A high dielectric constant (HDC) capacitive dielectric film is fabricated in a capacitor structure using relatively high pressure surface treatments. After forming the HDC capacitive dielectric film on a supporting bottom plate electrode structure, a surface treatment comprising oxid |
| 6787482 |
Method to form a DRAM capacitor using low temperature reoxidation |
September 7, 2004 |
| An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein th |
| 6703690 |
Apparatus for reducing isolation stress in integrated circuits |
March 9, 2004 |
| Mechanical stress is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride. The silicon nitride can be graded in a substantially linear or non-linear fashion. In o |
| 6690044 |
Approach to avoid buckling BPSG by using an intermediate barrier layer |
February 10, 2004 |
| A multilayer heterostructure is provided a planarization layer superjacent a semiconductor substrate. The planarization layer comprises tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass ("BPSG |
| 6667540 |
Method and apparatus for reducing fixed charge in semiconductor device layers |
December 23, 2003 |
| The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O.sub.3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to |
| 6635568 |
Refractory metal roughness reduction using high temperature anneal in hydrides or organo-silane |
October 21, 2003 |
| An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a conductively doped polysilicon gate |
| 6627508 |
Method of forming capacitors containing tantalum |
September 30, 2003 |
| The invention pertains to semiconductor circuit components and capacitors, and to methods of forming capacitors and semiconductor circuit components. In one aspect, the invention includes a method of forming a dielectric layer comprising: a) forming a first tantalum-comprising layer; and |
| 6620534 |
Film having enhanced reflow characteristics at low thermal budget |
September 16, 2003 |
| A method of forming a film having enhanced reflow characteristics at low thermal budget is disclosed, in which a surface layer of material is formed above a base layer of material, the surface layer having a lower melting point than the base layer. In this way, a composite film having |
| 6607946 |
Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O an |
August 19, 2003 |
| This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N.sub.2 O) and ozone (O.sub.3). The presence of O.sub.3 in the oxidizing ambiance greatly enhances the oxidation rate compa |
| 6602798 |
Method and apparatus for reducing isolation stress in integrated circuits |
August 5, 2003 |
| Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, such as dichlorosilane (DCS), mixe |
| 6593183 |
Semiconductor processing method using a barrier layer |
July 15, 2003 |
| A semiconductor processing method includes forming a conductively doped plug of semiconductive material within a first insulative layer. A barrier layer to out diffusion of dopant material from the semiconductive material is formed over the doped plug. Examples include undoped oxide, suc |
| 6592661 |
Method for processing wafers in a semiconductor fabrication system |
July 15, 2003 |
| A method of manufacturing semiconductor wafers in a processing chamber having at least one radiant heat source is provided. The method includes the steps of applying a predetermined amount of power to the radiant heat source and positioning a wafer within the processing chamber. The |
| 6573552 |
Method to form hemispherical grained polysilicon |
June 3, 2003 |
| A capacitor with Enhanced capacitance per cell area is provided. A container supported by a substrate is formed, followed by a first layer of undoped substantially amorphous silicon. Next, a layer of heavily doped amorphous silicon is formed on the first layer. A second layer of undoped |
| 6528436 |
Method of forming silicon nitride layer directly on HSG polysilicon |
March 4, 2003 |
| Silicon nitride layers, having thicknesses of 100 angstroms or less, are formed using chemical vapor deposition (CVD). Higher pressure and lower temperature deposition regimes are used to provide more uniform step coverage on complex topographies, such as hemispherical grain polysilicon. |
| 6525384 |
Conductor layer nitridation |
February 25, 2003 |
| Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin n |
| 6521507 |
Selective deposition of undoped silicon film seeded in chlorine and hydride gas for a stacked ca |
February 18, 2003 |
| A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using |
| 6518121 |
Boride electrodes and barriers for cell dielectrics |
February 11, 2003 |
| Titanium boride (TiB.sub.x), zirconium boride (ZrB.sub.x) and hafnium boride (HfB.sub.x) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrou |
| 6486020 |
High pressure reoxidation/anneal of high dielectric constant materials |
November 26, 2002 |
| A high dielectric constant (DC) capacitive dielectric film is fabricated in a capacitor structure using relatively high pressure surface treatments. After forming the DC capacitive dielectric film on a supporting bottom plate electrode structure, a surface treatment comprising oxidation, |
| 6462394 |
Device configured to avoid threshold voltage shift in a dielectric film |
October 8, 2002 |
| A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A |
| 6461982 |
Methods for forming a dielectric film |
October 8, 2002 |
| A method of forming a high dielectric oxide film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 and includes a plurality of oxygen vacancies present during the formation of the film. The high d |
| 6448133 |
Method to form a DRAM capacitor using low temperature reoxidation |
September 10, 2002 |
| An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein th |
| 6441466 |
Method and apparatus for reducing fixed charge in semiconductor device layers |
August 27, 2002 |
| The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O.sub.3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to |
| 6436818 |
Semiconductor structure having a doped conductive layer |
August 20, 2002 |
| Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a |
| 6414376 |
Method and apparatus for reducing isolation stress in integrated circuits |
July 2, 2002 |
| Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, such as dichlorosilane (DCS), mixe |
| 6404669 |
Reduced leakage DRAM storage unit |
June 11, 2002 |
| The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through |
| 6380103 |
Rapid thermal etch and rapid thermal oxidation |
April 30, 2002 |
| At least both a rapid thermal etch step and a rapid thermal oxidation step are performed on a semiconductor substrate in situ in a rapid thermal processor. A method including an oxidation step followed by an etch step may be used to remove contamination and damage from a substrate. A met |
| 6368887 |
Method of monitoring a process of manufacturing a semiconductor wafer including hemispherical gr |
April 9, 2002 |
| A method of monitoring a process of manufacturing a semiconductor wafer including an area of hemispherical grain polysilicon, the method comprising providing a probe including a liquid conductor; and performing a capacitance-voltage measurement with the probe, using a quasi-static me |
| 6337243 |
Semiconductor processing method of making a hemispherical grain (HSG) polysilicon layer |
January 8, 2002 |
| A semiconductor processing method of providing a hemispherical grain polysilicon layer atop a substrate includes, a) providing a substantially amorphous layer of silicon over a substrate at a selected temperature; b) raising the temperature of the substantially amorphous silicon layer to |
| 6333243 |
Method for growing field oxide to minimize birds' beak length |
December 25, 2001 |
| A method for forming field oxide isolation regions using oxygen implantation is described. An oxidation resistant layer such as silicon nitride is formed on a silicon substrate, and acts as an oxidation mask. An opening is then formed in the nitride layer, where field oxide is desire |
| 6325017 |
Apparatus for forming a high dielectric film |
December 4, 2001 |
| An apparatus for forming a high dielectric oxide film includes a controllable atomic oxygen source and a vaporized precursor source. A deposition chamber for receiving the atomic oxygen from the atomic oxygen source and vaporized precursor from the vaporized precursor source is used |
| 6316800 |
Boride electrodes and barriers for cell dielectrics |
November 13, 2001 |
| Titanium boride (TiB.sub.x), zirconium boride (ZrB.sub.x) and hafnium boride (HfB.sub.x) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrou |
| 6300243 |
Refractory metal roughness reduction using high temperature anneal in hydrides or organo-silane |
October 9, 2001 |
| An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a conductively doped polysilicon gate |
| 6282080 |
Semiconductor circuit components and capacitors |
August 28, 2001 |
| The invention pertains to semiconductor circuit components and capacitors. In another aspect, the invention includes a capacitor including: a) a first capacitor plate; b) a first tantalum-comprising layer over the first capacitor plate; c) a second tantalum-comprising layer over the firs |
| 6281511 |
Apparatus for forming materials |
August 28, 2001 |
| A semiconductor fabrication apparatus and methods for processing materials on a semiconductor wafer are disclosed. The fabrication apparatus is a processing chamber comprising: an ultraviolet radiation source and an infrared radiation source, the radiation sources symmetrically arranged |
