| Patent Number |
Title Of Patent |
Date Issued |
| 5140555 |
Semiconductor integrated device having uniform noise between a pair of undecided voltage portion |
August 18, 1992 |
| In a semiconductor integrated device having floating voltage portion pairs, a signal line crossing over or under the floating voltage portion pairs, and a non-floating voltage portion, a noise source equivalent to the signal line is provided between the floating voltage pairs and the |
| 5138419 |
Wafer scale integration device with dummy chips and relay pads |
August 11, 1992 |
| A wafer scale integration device comprises a plurality of real chips formed in the center portion of a wafer and a plurality of dummy chips formed in the circumference of the wafer. The dummy chips only include relay pads, some of the relay pads are used for relaying bonding wires of pow |
| 4982369 |
Self-refresh semiconductor memory device responsive to a refresh request signal |
January 1, 1991 |
| A semiconductor memory device carrying out a self-refresh operation in response to a refresh request signal. The device includes a memory cell array formed on a chip; a plurality of pseudo memory cells distributed and arranged on the chip, each having the same constitution as the memory |
| 4821238 |
Semiconductor memory device having test pattern generating circuit |
April 11, 1989 |
| A semiconductor memory device comprises an internal circuit including a memory circuit; a test pattern generating circuit; an element for receiving external signals supplied from the outside; and an input switching circuit connected between the test pattern generating circuit and the |
| 4802127 |
Output buffer circuit for a semiconductor memory device |
January 31, 1989 |
| A semiconductor memory device of multi-bit type which produces plural output signals corresponding to read-out data from one address at a time including memory device for storing data. In a plurality of output buffer stages for producing the output signals, the operation of the output |
| 4752914 |
Semiconductor integrated circuit with redundant circuit replacement |
June 21, 1988 |
| A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence |
| 4707806 |
Semiconductor integrated circuit device having fuse-type information storing circuit |
November 17, 1987 |
| A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and |
| 4592025 |
Information storing circuit using blown and unblown fuses |
May 27, 1986 |
| A circuit for storing information by blown and unblown fuses has at least two fuses per bit and an information output circuit. The information output circuit discriminates between the state in which all the fuses are unblown and the state in which at least one of the fuses is blown, and |
| 4473895 |
Semiconductor memory device |
September 25, 1984 |
| A semiconductor memory device (10), including a conventional redundancy memory array (12) therein, is disclosed. The redundancy memory array (12) is used for compensating data being stored in a defective memory cell (13') of main memory cells (11) located in the memory device (10). An |
| 4464750 |
Semiconductor memory device |
August 7, 1984 |
| A semiconductor memory device including a plurality of memory blocks (1-1, 1-2, 1-3, 1-4) each including a plurality of memory cells (C.sub.00, C.sub.01, . . . , C.sub.31,127). When test data is transmitted from one selected memory cell within each of the memory blocks to one of data bus |
