| Patent Number |
Title Of Patent |
Date Issued |
| RE39913 |
Method to control gate CD |
November 6, 2007 |
| The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle gen |
| 7598176 |
Method for photoresist stripping and treatment of low-k dielectric material |
October 6, 2009 |
| A plasma processing operation uses a gas mixture of N.sub.2 and H.sub.2 to both remove a photoresist film and treat a low-k dielectric material. The plasma processing operation prevents degradation of the low-k material by forming a protective layer on the low-k dielectric material. Carb |
| 7579248 |
Resolving pattern-loading issues of SiGe stressor |
August 25, 2009 |
| A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielec |
| 7531399 |
Semiconductor devices and methods with bilayer dielectrics |
May 12, 2009 |
| A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a |
| 7465634 |
Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with eleva |
December 16, 2008 |
| An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess for |
| 7436009 |
Via structures and trench structures and dual damascene structures |
October 14, 2008 |
| Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner |
| 7429769 |
Recessed channel field effect transistor (FET) device |
September 30, 2008 |
| A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of sour |
| 7410854 |
Method of making FUSI gate and resulting structure |
August 12, 2008 |
| Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stack height, removing |
| 7402866 |
Backside contacts for MOS devices |
July 22, 2008 |
| A semiconductor structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate dielectric over the first surface of the semiconductor substrate, a gate electrode over the gate dielectric, a source/drain region having at least |
| 7400401 |
Measuring low dielectric constant film properties during processing |
July 15, 2008 |
| A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrome |
| 7390753 |
In-situ plasma treatment of advanced resists in fine pattern definition |
June 24, 2008 |
| A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be e |
| 7378713 |
Semiconductor devices with dual-metal gate structures and fabrication methods thereof |
May 27, 2008 |
| Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second |
| 7373941 |
Wet cleaning cavitation system and method to remove particulate wafer contamination |
May 20, 2008 |
| A cavitation cleaning system and method for using the same to remove particulate contamination from a substrate including providing at least one substrate immersed in a cleaning solution said cleaning solution contained in a cleaning solution container. The container further includes |
| 7354847 |
Method of trimming technology |
April 8, 2008 |
| A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w.sub.1 |
| 7354524 |
Method and system for processing multi-layer films |
April 8, 2008 |
| A method of processing multi-layer films, the method including: (1) processing a plurality of layers according to selected parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the processing of th |
| 7341943 |
Post etch copper cleaning using dry plasma |
March 11, 2008 |
| A method for post-etch copper cleaning uses a hydrogen plasma with a trace gas additive constituting about 3-10 percent of the plasma by volume to clean a copper surface exposed by etching. The trace gas may be atomic nitrogen or other species having an atomic mass of 15 or greater. The |
| 7307009 |
Phosphoric acid free process for polysilicon gate definition |
December 11, 2007 |
| A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is |
| 7301645 |
In-situ critical dimension measurement |
November 27, 2007 |
| A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upo |
| 7294544 |
Method of making a metal-insulator-metal capacitor in the CMOS process |
November 13, 2007 |
| A method for fabricating an improved metal-insulator-metal capacitor is achieved. An insulating layer is provided overlying conducting lines on a semiconductor substrate. Via openings through the insulating layer to the conducting lines are filled with metal plugs. A first metal layer is |
| 7276417 |
Hybrid STI stressor with selective re-oxidation anneal |
October 2, 2007 |
| A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the |
| 7271448 |
Multiple gate field effect transistor structure |
September 18, 2007 |
| A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel sp |
| 7265060 |
Bi-level resist structure and fabrication method for contact holes on semiconductor substrates |
September 4, 2007 |
| An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique comb |
| 7265056 |
Method for forming novel BARC open for precision critical dimension control |
September 4, 2007 |
| A method for forming an opening in a semiconductor device is provided. In one embodiment, a bottom anti-reflective coating (BARC) layer is formed overlying an insulation layer of a substrate. A patterned photoresist layer including at least one opening therein is formed overlying the BAR |
| 7241674 |
Method of forming silicided gate structure |
July 10, 2007 |
| A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate |
| 7217663 |
Via hole and trench structures and fabrication methods thereof and dual damascene structures and |
May 15, 2007 |
| Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the |
| 7208331 |
Methods and structures for critical dimension and profile measurement |
April 24, 2007 |
| Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to th |
| 7172933 |
Recessed polysilicon gate structure for a strained silicon MOSFET device |
February 6, 2007 |
| A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in |
| 7148114 |
Process for patterning high-k dielectric material |
December 12, 2006 |
| A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the |
| 7141460 |
Method of forming trenches in a substrate by etching and trimming both hard mask and a photosens |
November 28, 2006 |
| A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anisotropically transf |
| 7122484 |
Process for removing organic materials during formation of a metal interconnect |
October 17, 2006 |
| A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelat |
| 7115526 |
Method for wet etching of high k thin film at low temperature |
October 3, 2006 |
| The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of |
| 7115450 |
Approach to improve line end shortening including simultaneous trimming of photosensitive layer |
October 3, 2006 |
| A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anisotropically transf |
| 7109085 |
Etching process to avoid polysilicon notching |
September 19, 2006 |
| A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the |
| 7092096 |
Optical scatterometry method of sidewall spacer analysis |
August 15, 2006 |
| A method of analyzing structural characteristics of sidewall spacers fabricated on a wafer is disclosed. A grating bar having a plurality of grating targets is provided. A theoretical optical scatterometry spectrum is generated by subjecting the grating targets to optical scatterometry. |
| 7078351 |
Photoresist intensive patterning and processing |
July 18, 2006 |
| A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask |
| 7074727 |
Process for improving dielectric properties in low-k organosilicate dielectric material |
July 11, 2006 |
| Low-k organosilicate dielectric material can be exposed to a series of reagents, including a halogenation reagent, an alkylation reagent, and a termination reagent, in order to reverse degradation of dielectric properties caused by previous processing steps. |
| 7067391 |
Method to form a metal silicide gate device |
June 27, 2006 |
| A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidew |
| 7067235 |
Bi-layer photoresist dry development and reactive ion etch method |
June 27, 2006 |
| A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure |
| 7060628 |
Method for fabricating a hard mask polysilicon gate |
June 13, 2006 |
| A method for forming a patterned silicon-containing layer is disclosed. The method includes providing a substrate, providing a polysilicon layer on the substrate, providing a hard mask layer on the polysilicon layer, patterning and etching the hard mask layer and etching the polysilicon |
| 7037849 |
Process for patterning high-k dielectric material |
May 2, 2006 |
| A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the |
| 7033518 |
Method and system for processing multi-layer films |
April 25, 2006 |
| A method of etching multi-layer films, the method including: (1) etching a plurality of layers according to etching parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the etching of the associated |
| 7029992 |
Low oxygen content photoresist stripping process for low dielectric constant materials |
April 18, 2006 |
| A plasma containing 5 10% oxygen and 90 95% of an inert gas strips photoresist from over a low-k dielectric material formed on or in a semiconductor device. The inert gas may be nitrogen, hydrogen, or a combination thereof, or it may include at least one of nitrogen, hydrogen, NH.sub |
| 7023042 |
Method of forming a stacked capacitor structure with increased surface area for a DRAM device |
April 4, 2006 |
| A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The g |
| 7022610 |
Wet cleaning method to eliminate copper corrosion |
April 4, 2006 |
| A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning |
| 7008878 |
Plasma treatment and etching process for ultra-thin dielectric films |
March 7, 2006 |
| A method for dry etching a dielectric layer including providing a substrate; forming at least one overlying dielectric layer over the substrate; subjecting the at least one overlying layer to a plasma oxidizing process; and, subjecting the at least one overlying layer to a plasma etc |
| 7008866 |
Large-scale trimming for ultra-narrow gates |
March 7, 2006 |
| Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to furthe |
| 6974730 |
Method for fabricating a recessed channel field effect transistor (FET) device |
December 13, 2005 |
| A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of sour |
| 6969688 |
Wet etchant composition and method for etching HfO2 and ZrO2 |
November 29, 2005 |
| A wet etchant solution composition and method for etching oxides of hafnium and zirconium including at least one solvent present at greater than about 50 weight percent with respect to an arbitrary volume of the wet etchant solution; at least one chelating agent present at about 0.1 weig |
| 6914007 |
In-situ discharge to avoid arcing during plasma etch processes |
July 5, 2005 |
| A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt |
| 6878639 |
Borderless interconnection process |
April 12, 2005 |
| A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer m |
