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Inventor:
Tang; Tien-Hao
Address:
Hsinchu, TW
No. of patents:
14
Patents:












Patent Number Title Of Patent Date Issued
8299532 ESD protection device structure October 30, 2012
An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in
7910998 Silicon controlled rectifier device for electrostatic discharge protection March 22, 2011
An SCR device includes a substrate, a plurality of isolation structures defining a first region and a second region in the substrate, an n well disposed in the substrate, an n type first doped region disposed in the first region in the substrate, a p type second doped region disposed in
7906810 LDMOS device for ESD protection circuit March 15, 2011
A LDMOS device for an ESD protection circuit is provided. The LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, a body region of the first conductivity type, first and second doped regions of the second conductivity type, an
7655980 Device for ESD protection circuit February 2, 2010
A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device fur
7638857 Structure of silicon controlled rectifier December 29, 2009
A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant
7217980 CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection May 15, 2007
An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivit
6894324 Silicon-on-insulator diodes and ESD protection circuits May 17, 2005
A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region the
6861680 Silicon-on-insulator diodes and ESD protection circuits March 1, 2005
A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof
6806160 Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation C October 19, 2004
A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and instead of a dummy gate. T
6653670 Silicon-on-insulator diodes and ESD protection circuits November 25, 2003
A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region the
6649944 Silicon-on-insulator diodes and ESD protection circuits November 18, 2003
A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region th
6521952 Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD pro February 18, 2003
An NMOS-trigger silicon controlled rectifier in silicon-on-insulator (SOI-NSCR) SOI-NSCR includes a P-type well and an N-type well. A first P.sup.+ doping region and a first N.sup.+ doping region are in the N-type well and form the anode of the SOI-NSCR. A second P.sup.+ doping region
6498357 Lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process December 24, 2002
A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and instead of a dummy gate. T
6465768 MOS structure with improved substrate-triggered effect for on-chip ESD protection October 15, 2002
An ESD protection device is formed on a P-type well, and has at least one NMOS, at least one first P.sup.+ diffusion region for electrically connecting to a P-well biasing circuit, at least one dummy gate between the NMOS and the first P.sup.+ diffusion region, at least one second P.










 
 
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