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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Tanaka; Kenichi
Address:
Nara, JP
No. of patents:
22
Patents:












Patent Number Title Of Patent Date Issued
5420079 Process for producing semiconductor device comprising two step annealing treatment May 30, 1995
The disclosed invention is a process for fabricating a semiconductor device comprising the steps of:forming a gate electrode;covering the gate electrode and surface of the substrate with a layer of silicon dioxide;etching the silicon dioxide layer using an RIE method and an HF etching me
5411904 Process for fabricating nonvolatile random access memory having a tunnel oxide film May 2, 1995
A nonvolatile random access memory comprising a nonvolatile random access memory unit having on a substrate an EEPROM having a tunnel oxide film and a floating gate, and a DRAM linked to the EEPROM, a thermal oxide film being selectively formed between the EEPROM and another EEPROM adjac
5401993 Non-volatile memory March 28, 1995
A non-volatile memory includes a single transistor having a semiconductor substrate, source and drain diffusion layers formed on a surface of the semiconductor substrate, and a gate electrode provided on the semiconductor substrate with a gate insulating film interposed between them.
5357460 Semiconductor memory device having two transistors and at least one ferroelectric film capacitor October 18, 1994
A semiconductor memory device which comprises unit memory cells each including two transistors each having a source/drain region and a gate electrode and one capacitor having a capacitor dielectric film, an upper electrode and a lower electrode, the gate electrode of each transistor
5331181 Non-volatile semiconductor memory July 19, 1994
A non-volatile semiconductor memory providing a semiconductor substrate including source and drain diffusion regions and a gate electrode, and an insulating film which is at least provided on the semiconductor substrate just below the gate electrode and has a smaller dielectric breakdown
5309386 Semiconductor memory with enhanced capacity May 3, 1994
A semiconductor memory wherein a plurality of cells are arranged in a longitudinal direction of active regions, each cell having a node electrode and a contact hole for the node electrode, and a bit line contact region and the active region by half at the least on a semiconductor sub
5299152 Anti-fuse memory device with switched capacitor setting method March 29, 1994
A semiconductor device includes memory cells each of which include a plurality of groups of an anti-fuse and a transistor connected in series; a capacitor including first and second electrodes, with the first electrode connected to a bit line of the memory cell; a first switch connec
5299151 Method for writing into semiconductor memory March 29, 1994
A method is provided for writing into a semiconductor memory which includes a MOS transistor formed on a semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor. The method includes the steps of applying a first voltag
5298446 Process for producing semiconductor device March 29, 1994
A process for producing a semiconductor device comprising the steps of:(a) on a semiconductor Si substrate having a gate electrode formed thereon through the intermediary of an SiO.sub.2 film,i) forming as side wall of SiO.sub.2 on the side of said gate electrode followed by formation of an
5290725 Semiconductor memory device and a method for producing the same March 1, 1994
A method for producing a semiconductor memory device including a volatile memory element, a non-volatile memory element, and a driver in combination on a silicon conductive substrate is provided. The volatile memory element is a DRAM and is disposed in and on a reverse-conductive well. A
5282159 Semiconductor memory with increased capacitive storage capabilities and reduced size January 25, 1994
A semiconductor memory includes a transistor and a capacitor which are formed on a semiconductor substrate, wherein the capacitor comprises in superposed layers a first capacitor composed of an impurity diffused layer formed in a surface layer of the semiconductor substrate, a first
5200356 Method of forming a static random access memory device April 6, 1993
A static random access memory device includes memory cells each having four MOS transistors and two load resistors which form a flip-flop circuit. The load resistor is formed by ion implantation of impurities in a predetermined region of an oxide film which is an extension of a gate
5181188 Semiconductor memory device January 19, 1993
A semiconductor memory device having memory cells in which a DRAM section and an EEPROM section are combined, and a transistor for transferring data between the DRAM and EEPROM sections is disclosed. The DRAM section includes a MOS transistor, and a capacitor one electrode of which is
5140552 Semiconductor memory device having a volatile memory device and a non-volatile memory device August 18, 1992
A semiconductor memory device comprising a DRAM, an EEPROM, a mode switch circuit for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer circuit for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one
5139964 Method for forming isolation region of semiconductor device August 18, 1992
An improved LOCOS method for forming an isolation region with a higher breakdown voltage and a reduced width in a semiconductor device, comprising the steps of:(a) forming on a silicon substrate a silicon nitride layer having a predetermined pattern and a tapered-slant side wall, between
5119163 Semiconductor device June 2, 1992
A semiconductor device includes memory cells each of which include a plurality of groups of an anti-fuse and a transistor connected in series; a capacitor including first and second electrodes, with the first electrode connected to a bit line of the memory cell; a first switch connec
5108783 Process for producing semiconductor devices April 28, 1992
A process for producing a semiconductor device including the steps of:(a) forming a trench in a semiconductor substrate at a portion thereof where an isolating zone is to be formed,(b) doping the substrate with an impurity element from the inner wall thereof defining the trench to form a hig
5075888 Semiconductor memory device having a volatile memory device and a non-volatile memory device December 24, 1991
A semiconductor memory device composed of a DRAM, an EEPROM, a mode switch means for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer means for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacit
5059550 Method of forming an element isolating portion in a semiconductor device October 22, 1991
A method for manufacturing a semiconductor device comprising:making a trench in a Si semiconductor substrate;forming on the surface of the substrate a thermal oxidation film a Si.sub.3 N.sub.4 film, and a SiO.sub.2 film by a chemical vapor deposition as a three-layered insulating film, in th
5049970 High resistive element September 17, 1991
A high resistive element is provided that constitutes an element of integrated circuits comprising an oxide film formed on a semiconductor substrate and a polysilicon film formed on the oxide film. The high resistive element is prepared by ion injection of silicon ions and conductive
5043946 Semiconductor memory device August 27, 1991
A semiconductor memory device comprising a DRAM, an EEPROM, a mode switch for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer circuit for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacitor, a
4803662 EEPROM cell February 7, 1989
An EEPROM cell for a memory device comprises a pair of bit lines each including a floating-gate MOS transistor such that a selected one of the transistors can be charged while the other is in uncharged condition by applying a higher voltage to a corresponding one of the bit lines and a










 
 
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