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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Takahshi; Yasuhiko
Address:
Higashiyamato, JP
No. of patents:
5
Patents:












Patent Number Title Of Patent Date Issued
7972920 Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a July 5, 2011
Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate
7701020 Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a April 20, 2010
Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate
7495289 Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a February 24, 2009
Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate
7190031 Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a March 13, 2007
Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate
7161215 Semiconductor memory device and method of manufacturing the same, a method of manufacturing a ve January 9, 2007
Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate










 
 
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