| Patent Number |
Title Of Patent |
Date Issued |
| 7586130 |
Vertical field effect transistor using linear structure as a channel region and method for fabri |
September 8, 2009 |
| A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate el |
| 7564073 |
CMOS and HCMOS semiconductor integrated circuit |
July 21, 2009 |
| A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions |
| 7554139 |
Semiconductor manufacturing method and semiconductor device |
June 30, 2009 |
| A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitio |
| 7473967 |
Strained channel finFET device |
January 6, 2009 |
| A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first |
| 7235830 |
Semiconductor device and process for manufacturing the same |
June 26, 2007 |
| The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3) |
| 7205586 |
Semiconductor device having SiGe channel region |
April 17, 2007 |
| A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high |
| 7170110 |
Semiconductor device and method for fabricating the same |
January 30, 2007 |
| A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally he |
| 7135721 |
Heterojunction bipolar transistor having reduced driving voltage requirements |
November 14, 2006 |
| The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter regio |
| 7126170 |
MISFET for reducing leakage current |
October 24, 2006 |
| A MISFET according to this invention includes: a substrate having a semiconductor layer; an active region formed in the semiconductor layer; a gate insulator formed on the active region; a gate formed on the gate insulator; and a source region and a drain region, wherein: the active |
| 7119417 |
Semiconductor device and fabrication method thereof |
October 10, 2006 |
| A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode i |
| 7087473 |
Method of forming conventional complementary MOS transistors and complementary heterojunction MO |
August 8, 2006 |
| A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions |
| 7084484 |
Semiconductor integrated circuit |
August 1, 2006 |
| A semiconductor integrated circuit including a plurality of bipolar transistors that are produced by forming, in a plurality of transistor-producing regions, a first conductive type emitter layer on the front surface side of a second conductive type base layer that is formed on the s |
| 7084026 |
Semiconductor device and method for fabricating the same |
August 1, 2006 |
| A region of an Si layer 15 located between source and drain regions 19 and 20 is an Si body region 21 which contains an n-type impurity of high concentration. An Si layer 16 and an SiGe layer 17 are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of |
| 6987065 |
Method of manufacturing self aligned electrode with field insulation |
January 17, 2006 |
| The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3) |
| 6984844 |
Semiconductor device having heterojunction type MIS transistor which can operate at reduced volt |
January 10, 2006 |
| A semiconductor device according to the invention includes: a semiconductor layer (10 15); a gate insulator (16) provided on the semiconductor layer; a gate electrode (17) provided on the gate insulator; a source region (20a) and a drain region (20b), which are of a first conductivit |
| 6939772 |
Bipolar transistor and fabrication method thereof |
September 6, 2005 |
| A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 |
| 6917075 |
Semiconductor device |
July 12, 2005 |
| A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed i |
| 6876045 |
Semiconductor device and process for manufacturing the same |
April 5, 2005 |
| This specification relates to a process for manufacturing a semiconductor device, comprising the steps of: forming a lower gate electrode film on a semiconductor substrate 10 via a gate insulating film 11; forming an upper gate electrode film on the lower gate electrode film, the upper g |
| 6872989 |
Semiconductor device and method for fabricating the same |
March 29, 2005 |
| A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats |
| 6858454 |
Method for measuring semiconductor constituent element content and method for manufacturing a se |
February 22, 2005 |
| A method for measuring semiconductor constituent element content utilizes the steps of: obtaining a film thickness of an SiGeC layer formed on a semiconductor substrate by evaluation using spectroscopic ellipsometry; measuring infrared absorption spectrum of the SiGeC layer; and obtainin |
| 6852602 |
Semiconductor crystal film and method for preparation thereof |
February 8, 2005 |
| A multi-layer film 10 is formed by stacking a Si.sub.1-x1-y1 Ge.sub.x1 C.sub.y1 layer (0.ltoreq.x1<1 and 0<y1<1) having a small Ge mole fraction, e.g., a Si.sub.0.785 Ge.sub.0.2 C.sub.0.015 layer 13, and a Si.sub.1-x2-y2 Ge.sub.x2 C.sub.y2 layer (0<x2.ltoreq.1 and 0.ltore |
| 6828602 |
Bipolar transistor and method manufacture thereof |
December 7, 2004 |
| A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 |
| 6821870 |
Heterojunction bipolar transistor and method for fabricating the same |
November 23, 2004 |
| A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band |
| 6821856 |
Method of manufacturing semiconductor device having source/drain regions included in a semicondu |
November 23, 2004 |
| A semiconductor device comprises an Si substrate, an isolation insulating film formed on the Si substrate, an Si layer formed on the Si substrate, a gate oxide film formed on the Si layer, a gate electrode formed on the gate oxide film, a sidewall formed on the side face of the gate elec |
| 6815735 |
Semiconductor device |
November 9, 2004 |
| A semiconductor layer 30 of a graded SiGe-HDTMOS is constructed of an upper Si film 12, an Si buffer layer 13, an Si.sub.1-x Ge.sub.x film 14 and an Si cap layer 15. The region between a source region 20a and drain region 20b of the semiconductor layer 30 includes a high concentration n- |
| 6800532 |
Method of manufacturing a semiconductor device comprising a bipolar transistor and a variable ca |
October 5, 2004 |
| A variable capacitor includes an N.sup.+ layer including a variable capacitance region, a P.sup.+ layer epitaxially grown on the N.sup.+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffu |
| 6781163 |
Heterojunction field effect transistor |
August 24, 2004 |
| A region of an Si layer (15) located between source and drain regions (19 and 20) is an Si body region (21) which contains an n-type impurity of high concentration. An Si layer (16) and an SiGe layer (17) are, in an as grown state, undoped layers into which no n-type impurity is doped. |
| 6759697 |
Heterojunction bipolar transistor |
July 6, 2004 |
| The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. T |
| 6753555 |
DTMOS device having low threshold voltage |
June 22, 2004 |
| A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high |
| 6737684 |
Bipolar transistor and semiconductor device |
May 18, 2004 |
| There is provided a MQB layer as a multi-quantum barrier portion composed of well layers and barrier layers that are formed of extremely thin films having different compositions and alternately stacked. This enhances an effective barrier height by using the phenomenon that holes likely t |
| 6713790 |
Semiconductor device and method for fabricating the same |
March 30, 2004 |
| In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on |
| 6674150 |
Heterojunction bipolar transistor and method for fabricating the same |
January 6, 2004 |
| A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band |
| 6642607 |
Semiconductor device |
November 4, 2003 |
| A variable capacitor includes an N.sup.+ layer including a variable capacitance region, a P.sup.+ layer epitaxially grown on the N.sup.+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffu |
| 6512252 |
Semiconductor device |
January 28, 2003 |
| A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high |
| 6492711 |
Heterojunction bipolar transistor and method for fabricating the same |
December 10, 2002 |
| A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band |
| 6472685 |
Semiconductor device |
October 29, 2002 |
| A first silicon layer (Si layer), a second silicon layer (Si.sub.1 C.sub.y layer) containing carbon and a third silicon layer not containing carbon are stacked in this order on a silicon substrate. Since the lattice constant of the Si.sub.1-y C.sub.y layer is smaller than that of the Si |
| 6455364 |
Semiconductor device and method for fabricating the same |
September 24, 2002 |
| In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on |
| 6399993 |
Semiconductor device and method for fabricating the same |
June 4, 2002 |
| In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base |
| 6277657 |
Apparatus for fabricating semiconductor device and fabrication method therefor |
August 21, 2001 |
| A crystal growing apparatus comprises a vacuum vessel, a heating lamp, a lamp controller for controlling the heating lamp, a gas inlet port, a flow rate adjuster for adjusting the flow rate of a gas, a pyrometer for measuring the temperature of a substrate, and a gas supply unit for |
