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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Tago; Kazutami
Address:
Hitachinaka, JP
No. of patents:
8
Patents:












Patent Number Title Of Patent Date Issued
7737023 Method of manufacture of semiconductor integrated circuit device and semiconductor integrated ci June 15, 2010
In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes
7442651 Plasma etching method October 28, 2008
An etching technique capable of applying etching at high selectivity to a transition metal element-containing electrode material layer which is formed on or above a dielectric material layer made of a high-dielectric-constant or "high-k" insulator is provided. To this end, place a wo
7419902 Method of manufacture of semiconductor integrated circuit September 2, 2008
In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes
6309980 Semiconductor integrated circuit arrangement fabrication method October 30, 2001
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta
6074958 Semiconductor integrated circuit arrangement fabrication method June 13, 2000
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta
5962347 Semiconductor integrated circuit arrangement fabrication method October 5, 1999
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta
5895586 Plasma processing apparatus and plasma processing method in which a part of the processing chamb April 20, 1999
There are provided a plasma processing apparatus and a plasma processing method which are suitable for processing a processed substance using a gas plasma containing fluorine atoms.Structural materials used for a high vacuum processing chamber of a plasma processing apparatus are aluminu
5874013 Semiconductor integrated circuit arrangement fabrication method February 23, 1999
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta










 
 
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