| Patent Number |
Title Of Patent |
Date Issued |
| 7613951 |
Scaled time trace |
November 3, 2009 |
| The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is issued one clock. One frame of trace data is generated for each functional clock issued. A valid signal may be implemented cha |
| 7607047 |
Method and system of identifying overlays |
October 20, 2009 |
| A method and system of identifying overlays. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system (the traced program comprising a plurality of overlay programs), obtaining values indicative of which of the plurality of ov |
| 7603589 |
Method and system for debugging a software program |
October 13, 2009 |
| A profiling system. At least some of the illustrative embodiments are integrated circuit devices comprising a processing circuit configured to execute a target program (the processing circuit having a plurality of registers), a trace system operatively coupled to the processing circuit |
| 7603521 |
Prioritizing caches having a common cache level |
October 13, 2009 |
| An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches having a common cache level. The software also causes the processor to prioritize th |
| 7593841 |
Emulation export sequence with distributed control |
September 22, 2009 |
| Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information bloc |
| 7590912 |
Using a chip as a simulation engine |
September 15, 2009 |
| The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and issues one gated clock to the functional logic. This creates a new CPU state and causes the |
| 7590894 |
Method of translating system events into signals for activity monitoring |
September 15, 2009 |
| Disclosed herein is a system and method for receiving encoded events from a system that is being debugged or profiled. The encoded events are input to a decoder in order to decode the encoded events, wherein the decoder is configured to selectively adjust the bandwidth of decoded events. |
| 7590893 |
Recording control point in trace receivers |
September 15, 2009 |
| A trace receiver with multiple recording interfaces may be used to record the same input. The historical control point for starting and stopping trace recording is placed very near the front end. A new control point further from the front end allows the front end to continue operation |
| 7571366 |
Sequential signals selecting mode and stopping transfers of interface adaptor |
August 4, 2009 |
| A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermined sequence of the |
| 7562259 |
Distributed depth trace receiver |
July 14, 2009 |
| Input processing limitations may be solved by placing multiple units in series, with each unit recording some portion of the incoming data. This requires the generation of simultaneous actions across units operating in series, with both the data recording and user command execution happe |
| 7561596 |
Systems and methods for multiplexing and demultiplexing multiple data sources |
July 14, 2009 |
| The present disclosure describes systems and methods for multiplexing multiple data sources Some illustrative embodiments include a method for combining multiple data sources, including building one or more single-source data words by iteratively selecting a data source, writing data |
| 7555682 |
Distributed width trace receiver |
June 30, 2009 |
| Input processing limitations may be solved by placing two units in parallel, with each unit recording some portion of the incoming data. This requires the generation of simultaneous actions across units operating in parallel, with both the data recording and user command execution ha |
| 7555681 |
Multi-port trace receiver |
June 30, 2009 |
| A trace receiver with multiple recording interfaces is used to record the same input. This configuration may provide multiple recording interfaces and multiple recording channels. The recording channels may be in a single unit or in multiple units. Separate out of phase clocks may be |
| 7552360 |
Debug and test system with format select register circuitry |
June 23, 2009 |
| A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register |
| 7519497 |
Apparatus and method for state selectable trace stream generation |
April 14, 2009 |
| A trace test and debug system for a target processor generates a program counter trace stream, a timing trace stream and a data trace stream. The target processor has three states, a program code execution state, an interrupt service routine code execution state, and a state where code |
| 7519111 |
Apparatus and method for providing system and test clock signals to an integrated circuit on a s |
April 14, 2009 |
| In a configuration testing integrated circuits, the system clock signals are forced to the same frequency as the test clock signals. When the test clock signals and the system clock signals have the same frequency, both clock signals can applied to the integrated circuit through a single |
| 7464311 |
Apparatus and method for device selective scans in data streaming test environment for a process |
December 9, 2008 |
| In a multi processor environment wherein the processors are capable of implementing a streaming data mode of operation, a technique is provided that reduces the number of bits shifted through the scan chain necessary to select a processor for operating in the streaming data mode. All tes |
| 7463653 |
Apparatus and method for compression of the timing trace stream |
December 9, 2008 |
| In a test and debug system, a plurality of trace streams, including a timing trace stream, are transmitted from the target processing unit to the host processing unit for analysis. The timing trace stream, the trace stream that indicates activity or non-activity of the program counter |
| 7428666 |
Apparatus and method for trace stream identification of a pipeline flattener secondary code flus |
September 23, 2008 |
| When an INTERRUPT SERVICE ROUTINE (SECONDARY) CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has |
| 7417567 |
High speed data recording with input duty cycle distortion |
August 26, 2008 |
| Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captur |
| 7404106 |
Apparatus and method for reporting program halts in an unprotected pipeline at non-interruptible |
July 22, 2008 |
| In a target processor having a non-protected pipeline, the execution code is typically provided with interruptible code portions and with non-interruptible code portions. The non-interruptible code portions prevent implementation of a real time interrupt that would corrupt the code s |
| 7392431 |
Emulation system with peripherals recording emulation frame when stop generated |
June 24, 2008 |
| In-circuit-emulation of an integrated circuit includes a digital data processor capable of executing program instructions. A first debug event is detected during normal program execution. The causes the in-circuit-emulation to suspend program execution except for real time interrupts |
| 7391344 |
High speed data recording with input duty cycle distortion |
June 24, 2008 |
| Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captur |
| 7334114 |
Real-time monitoring, alignment, and translation of CPU stalls or events |
February 19, 2008 |
| A system and method of tracing a group of processor events in real-time in order to enable a programmer to debug and profile the operation and execution of code on the processor. This may be accomplished by running one or more traces on the same or different groups of processor events in |
| 7325169 |
Apparatus and method for trace stream identification of multiple target processor events |
January 29, 2008 |
| When a plurality of simultaneous, preselected target processor events are detected, a multiple-event sync marker is generated that identifies the preselected events and relates the occurrence of these events to timing trace stream. The sync marker for the plurality of preselected events |
| 7318176 |
Tracing program counter addresses using native program counter format and instruction count form |
January 8, 2008 |
| A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program co |
| 7318017 |
Collecting and exporting on-chip data processor trace and timing information with differing coll |
January 8, 2008 |
| Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is re-arranged into a plurality of second information blocks which differ in size from the first information blocks. A sequence of the |
| 7315808 |
Correlating on-chip data processor trace information for export |
January 1, 2008 |
| In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a synchronization marker is inserted into the program counter trace stream. Trace information indicative of a data processing operation |
| 7310749 |
Apparatus and method for trace stream identification of a processor debug halt signal |
December 18, 2007 |
| When a DEBUG HALT signal is generated in a target processor during a test procedure, a debug halt sync marker is generated in a program counter trace stream. The debug halt sync marker includes a plurality of packets, the packets identifying that the sync marker is the result of a DEBUG |
| 7299386 |
Apparatus and method for detecting address characteristics for use with a trigger generation uni |
November 20, 2007 |
| A comparator unit includes first and second comparator components. The first and second comparator components exchange signals and generate signals when certain characteristics are met. The comparator unit finds application a target processor for generating event signals can be used |
| 7274313 |
High speed data recording with input duty cycle distortion |
September 25, 2007 |
| Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captur |
| 7237151 |
Apparatus and method for trace stream identification of a processor reset |
June 26, 2007 |
| When a RESET signal is generated in a target processor during a test procedure, a reset sync marker is generated in a program counter trace stream. The reset sync marker includes a plurality of packets, the packets identifying that the reset sync marker is the result of a RESET signa |
| 7225365 |
Apparatus and method for identification of a new secondary code start point following a return f |
May 29, 2007 |
| When a NEW SECONDARY CODE EXECUTION START POINT signal is generated in a target processor during a test procedure after the return from an interrupt service routine (i.e., an original secondary code sequence), a sync marker is generated in a program counter trace stream. The sync mar |
| 7210072 |
Apparatus and method for trace stream identification of a pipeline flattener primary code flush |
April 24, 2007 |
| When a PROGRAM CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of th |
| 7209058 |
Trace receiver data compression |
April 24, 2007 |
| A method repacks variable width trace data into a different packet length previous to being stored into memory. In order to conserve bandwidth, the trace data may also be compressed during transmission by eliminating the transmission of packets that have the same value. |
| 7206734 |
Exporting on-chip data processor trace information with variable proportions of control and data |
April 17, 2007 |
| Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information bloc |
| 7113902 |
Data processing condition detector with table lookup |
September 26, 2006 |
| In support of data processing emulation, a data processing condition indicated by a predetermined number of digital data processing signals can be detected by applying the digital data processing signals to a lookup table (LUT) that is programmable according to how the digital data p |
| 7089437 |
Apparatus for determining power consumed by a bus of a digital signal processor using counted nu |
August 8, 2006 |
| In order to measure the power consumed by a bus in a digital signal processor, each bus conductor has a lead electrically coupled thereto. The lead is coupled to apparatus that provides a signal each time the logic state of the bus is changed. The total number of logic signal changes |
| 7076419 |
Using sign extension to compress on-chip data processor trace and timing information for export |
July 11, 2006 |
| An emulation parameter indicative of a data processing operation performed by a data processor is exported from the data processor. The parameter value is provided as a plurality of digital bits. After determining that the bits of a first group within the plurality of bits all have the s |
| 7047451 |
Tracing program counter addresses using native program counter format and instruction count form |
May 16, 2006 |
| A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program co |
| 7043418 |
Synchronizing on-chip data processor trace and timing information for export |
May 9, 2006 |
| Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of emulation trace information indicative of data processing operations performed by the data processor is provided. A stream o |
| 7020600 |
Apparatus and method for improvement of communication between an emulator unit and a host device |
March 28, 2006 |
| In order to reduce the traffic over the communication bus between the host processing unit and an emulator server unit during the test of a target processing unit, the commands are divided into groups of test commands. A group of commands is transferred to the emulator server unit and st |
| 6996747 |
Program counter trace stack, access port, and serial scan path |
February 7, 2006 |
| A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations. |
| 6985848 |
Obtaining and exporting on-chip data processor trace and timing information |
January 10, 2006 |
| An emulation controller (12) located externally of an integrated circuit (14) can be provided with timing information indicative of operation of an internal clock of the integrated circuit that drives internal data processing activity of the integrated circuit. In response to each cycle |
| 6981178 |
Separation of debug windows by IDS bit |
December 27, 2005 |
| A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon detection of an interrupt. The interrupt during debug bit has a first digital state if the central processing unit is in a debug h |
| 6948155 |
Little offset in multicycle event maintaining cycle accurate tracing of stop events |
September 20, 2005 |
| A method of tracing activity of a data processor includes collecting and transmitting trace data. An epause marker is embedded in the trace stream upon detection of an emulation halt. This epause marker includes a little offset indicating a number of latency instructions within trace col |
| 6947884 |
Scan interface with TDM feature for permitting signal overlay |
September 20, 2005 |
| A scan interface that includes control signals (TRST, TMS, TCK) and data signals (TDI, TDO) normally carried by respective signal paths of the scan interface can be used to carry signals other than signals of the scan interface. A first signal (TMS) and a second signal (TDO) can be time |
| 6928403 |
Automatic detection of connectivity between an emulator and a target device |
August 9, 2005 |
| Connectivity between an emulation controller and a plurality of target devices can be automatically detected. After the target devices (Chip1, ChipN) and the emulation controller (12) tri-state respective terminals thereof, one of the target devices drives a predetermined logic level on |
| 6920416 |
Electronic systems testing employing embedded serial scan generator |
July 19, 2005 |
| An electronic system includes electronic circuitry to be tested having serial scan shift register latches, and a serial scan generator embedded in the electronic system upon manufacture and connected to the serial scan shift register latches of the electronic circuitry to facilitate test |
| 6912675 |
Using selective omission to compress on-chip data processor trace and timing information for exp |
June 28, 2005 |
| Parameter values of an emulation parameter that is indicative of a data processing operation performed by a data processor are exported from the data processor. In response to detection of a condition wherein a first portion of a first parameter value is identical to a corresponding port |
