| Patent Number |
Title Of Patent |
Date Issued |
| 7462546 |
Collector tailored structures for integration of binary junction transistors |
December 9, 2008 |
| A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic dilute mask is em |
| 7135397 |
Method and system for packaging ball grid arrays |
November 14, 2006 |
| According to one embodiment of the invention, a method of packaging ball grid arrays includes providing a substrate having a plurality of holes formed therein. Each hole is associated with a respective one of a plurality of contact pads formed on a first surface of the substrate. The |
| 7087479 |
Method of forming integrated circuit contacts |
August 8, 2006 |
| Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (13 |
| 7084494 |
Semiconductor package having integrated metal parts for thermal enhancement |
August 1, 2006 |
| A semiconductor device comprising a metallic leadframe (103) with a first surface (103a) and a second surface (103b). The leadframe includes a chip pad (104) and a plurality of segments (107); the chip pad is held by a plurality of straps (105), wherein each strap has a groove (106). A c |
| 7034379 |
Carbide emitter mask etch stop |
April 25, 2006 |
| Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbide layer provides an etch stop |
| 6909125 |
Implant-controlled-channel vertical JFET |
June 21, 2005 |
| We disclose the structure of an electronic device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has, near the top surface, a buried layer that is electrically communicable to a drain terminal. The device has a body |
| 6890836 |
Scribe street width reduction by deep trench and shallow saw cut |
May 10, 2005 |
| In a method to singulate a semiconductor wafer (100) into chips, trench streets (107) of predetermined depth (105a) are formed across the first, active wafer surface (102) to define the outline of the chips (101). Thereafter, the fabrication of the active first wafer surface is completed |
| 6861678 |
Double diffused vertical JFET |
March 1, 2005 |
| We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portio |
| 6847106 |
Semiconductor circuit with mechanically attached lid |
January 25, 2005 |
| One aspect of the invention is a semiconductor circuit comprising a semiconductor die electrically connected to a package substrate through a plurality of electrical contacts. A lid above and substantially parallel to the top surface of the die forms a portion of the semiconductor circui |
| 6833300 |
Method of forming integrated circuit contacts |
December 21, 2004 |
| Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). |
| 6787397 |
Semiconductor device protective overcoat with enhanced adhesion to polymeric materials and metho |
September 7, 2004 |
| An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging-semiconductor devices, and within the passivating film layers, including the following sequence of materials deposited by PECVD proces |
| 6780662 |
Selective deposition of emissive layer in electroluminescent displays |
August 24, 2004 |
| A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88) of a microeffusion cell (86). The method then provides for transporting the substrate (40) across the port (88) at a substanti |
| 6656811 |
Carbide emitter mask etch stop |
December 2, 2003 |
| Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbide layer provides an etch stop for |
| 6580170 |
Semiconductor device protective overcoat with enhanced adhesion to polymeric materials |
June 17, 2003 |
| An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging semiconductor devices, and within the passivating film layers, including the following sequence of materials deposited by PECVD proces |
| 6555476 |
Silicon carbide as a stop layer in chemical mechanical polishing for isolation dielectric |
April 29, 2003 |
| Silicon carbide is used for a hardmask for the isolation dielectric etch and also serves as an etch stop for chemical-mechanical polishing. Alternatively, silicon carbonitride or silicon carboxide can be used. |
| 6552375 |
Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use o |
April 22, 2003 |
| The present invention relates to a heterojunction bipolar transistor, and comprises a collector region, and a graded profile SiGe base layer overlying the collector region. The transistor further comprises a diffusion blocking layer overlying the graded profile SiGe base layer, and a |
| 6537607 |
Selective deposition of emissive layer in electroluminescent displays |
March 25, 2003 |
| A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88) of a microeffusion cell (86). The method then provides for transporting the substrate (40) across the port (88) at a substanti |
| 6528426 |
Integrated circuit interconnect and method |
March 4, 2003 |
| An inlaid interconnect fabrication method using a silicon carbide polish stop layer for protection of mechanically weak dielectric such as porous silicon dioxide (xerogel) during chemical mechanical polishing. |
| 6503838 |
Integrated circuit isolation of functionally distinct RF circuits |
January 7, 2003 |
| A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including forming a portion of an isolation region to expose a first area of the substrate, depositing a mask layer over the integrated circuit including |
| 6455393 |
Air bridge/dielectric fill inductors |
September 24, 2002 |
| A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including patterning and etching a portion of at least one of said isolation regions to expose a first area of said substrate, depositing a mask layer ove |
| 6420933 |
Low distortion current-to-current converter |
July 16, 2002 |
| A current-to-current impedance converter re-circulates the driver transistor collector current back into the output current path to generate an error current that has two portions including a DC offset portion and a second order in 1/.beta. portion. Since the error current has no first |
| 6417523 |
Organic edge emitting diode with light guide and pixel isolation |
July 9, 2002 |
| An edge emitter (12) includes a diode array (20) with an emissive edge (22). The diode array (20) is formed on a substrate layer (24) that includes integrated driver circuits (23) to power the diode array (20). Dielectric posts (26) are formed on the substrate layer to provide optical |
| 6376859 |
Variable porosity porous silicon isolation |
April 23, 2002 |
| Varying the porosity through the thickness of a porous silicon layer allows conflicting needs to be met by the same layer: a low porosity surface layer allows a high-quality epitaxial layer of silicon to be grown, or can provide structural support, while greater porosity in other portion |
| 6376285 |
Annealed porous silicon with epitaxial layer for SOI |
April 23, 2002 |
| An epitaxial layer of silicon is grown on a layer of partially-oxidized porous silicon, then covered by a capping layer which provides structural support and prevents oxidation of the epitaxial layer. A high-temperature anneal allows the partially oxidized silicon layer to separate into |
| 6362065 |
Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use o |
March 26, 2002 |
| The present invention relates to a method of forming a bipolar transistor or a heterojunction bipolar transistor. The method comprises forming a collector region associated with a semiconductor substrate, and forming a base region base region over at least a portion of the collector regi |
| 6262445 |
SiC sidewall process |
July 17, 2001 |
| The use of silicon carbide to form sidewall spacers allows the use of a lower temperature deposition step, and provides greater etch selectivity with respect to oxide. |
| 6261892 |
Intra-chip AC isolation of RF passive components |
July 17, 2001 |
| A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including forming a portion of at least one of the isolation regions to expose a first area of the substrate, depositing a mask layer over the integrated |
| 6255211 |
Silicon carbide stop layer in chemical mechanical polishing over metallization layers |
July 3, 2001 |
| Silicon carbide (SiC) is used as the stop layer for the chemical-mechanical polishing used to planarize the surface of interlevel dielectrics, making the resistance of the vias more uniform. Alternatively, silicon carbonitride or silicon carboxide can be used in place of silicon carbide. |
| 6197654 |
Lightly positively doped silicon wafer anodization process |
March 6, 2001 |
| A method of anodizing a lightly doped wafer wherein there is provided a lightly p-typed doped silicon wafer having a frontside and a backside. A p-type region is formed on the backside doped sufficiently to avoid inversion to n-type when a later applied current density of predetermined |
| 6103590 |
SiC patterning of porous silicon |
August 15, 2000 |
| A method of selectively forming porous silicon regions (106) in a silicon substrate (100). A masking layer (104) of SiC is deposited by PECVD over the substrate (100) using an organosilicon precursor gas such as trimethylsilane, silane/methane, or tetramethylsilane at a temperature b |
