| Patent Number |
Title Of Patent |
Date Issued |
| 6140188 |
Semiconductor device having load device with trench isolation region and fabrication thereof |
October 31, 2000 |
| A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up |
| 6133111 |
Method of making photo alignment structure |
October 17, 2000 |
| A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment st |
| 5993040 |
Well-based method for achieving low capacitance diffusion pattern filling |
November 30, 1999 |
| An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of well regions on a semiconductor substrate. The present invention also determines the locations of interconnect li |
| 5923947 |
Method for achieving low capacitance diffusion pattern filling |
July 13, 1999 |
| An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of active diffusion regions on a semiconductor substrate. The present invention also determines the locations of |
| 5877562 |
Photo alignment structure |
March 2, 1999 |
| A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment st |
| 5811346 |
Silicon corner rounding in shallow trench isolation process |
September 22, 1998 |
| A semiconductor device isolating structure and method for forming such a structure. In one embodiment, an opening is formed through a mask layer overlying a semiconductor substrate. A trench of a desired depth is then etched into the semiconductor substrate at the area of the semiconduct |
