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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Sung; Hung-Cheng
Address:
Hsinchu, TW
No. of patents:
84
Patents:


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Patent Number Title Of Patent Date Issued
7951670 Flash memory cell with split gate structure and method for forming the same May 31, 2011
A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface
7880217 Programmable non-volatile memory (PNVM) device February 1, 2011
A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating gate electrode on the g
7667261 Split-gate memory cells and fabrication methods thereof February 23, 2010
Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a sou
7652318 Split-gate memory cells and fabrication methods thereof January 26, 2010
Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a sou
7608884 Scalable split-gate flash memory cell with high source-coupling ratio October 27, 2009
A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is for
7557402 High write and erase efficiency embedded flash cell July 7, 2009
An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective
7417278 Method to increase coupling ratio of source to floating gate in split-gate flash August 26, 2008
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
7335941 Uniform channel programmable erasable flash EEPROM February 26, 2008
A new method to form a split gate for a flash device in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A film is deposited overlying the substrate. The film comprises a second dielectric layer overlying a first dielectric layer
7326994 Logic compatible non-volatile memory cell February 5, 2008
A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common f
7226828 Architecture to monitor isolation integrity between floating gate and source line June 5, 2007
A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide lay
7176083 High write and erase efficiency embedded flash cell February 13, 2007
An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective
7056791 Method of forming an embedded flash memory device June 6, 2006
A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulating layer is formed on
7001809 Method to increase coupling ratio of source to floating gate in split-gate flash February 21, 2006
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6881629 Method to make minimal spacing between floating gates in split gate flash April 19, 2005
A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is
6878986 Embedded flash memory cell having improved programming and erasing efficiency April 12, 2005
A memory cell including a substrate having a source region; a floating gate structure disposed over the substrate and associated with the source region; and a source coupling enhancement structure covering an exposed portion of the floating gate structure and extending to the source regi
6872667 Method of fabricating semiconductor device with separate periphery and cell region etching steps March 29, 2005
Methods of fabricating semiconductor devices using separate periphery and cell region etching steps are provided. A substrate is provided, wherein the substrate has a cell region and a periphery region separated by a shallow trench isolation (STI). The STI is filled with a dielectric
6849499 Process for flash memory cell February 1, 2005
A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by
6828183 Process for high voltage oxide and select gate poly for split-gate flash memory December 7, 2004
A process for forming a high voltage oxide (HV) and a select gate poly for a split-gate flash memory is disclosed. The general difficulty of forming oxides of two different thicknesses for two different areas on the same substrate is alleviated by forming an HV oxide layer over the entir
6819593 Architecture to suppress bit-line leakage November 16, 2004
A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each sub
6753569 Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolati June 22, 2004
A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a "smiling" gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls
6649489 Poly etching solution to improve silicon trench for low STI profile November 18, 2003
A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the
6635922 Method to fabricate poly tip in split gate flash October 21, 2003
A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the mini
6573555 Source side injection programming and tip erasing P-channel split gate flash memory cell June 3, 2003
A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a con
6569736 Method for fabricating square polysilicon spacers for a split gate flash memory device by multi- May 27, 2003
A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as
6559501 Method for forming split-gate flash cell for salicide and self-align contact May 6, 2003
A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an
6538277 Split-gate flash cell March 25, 2003
A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over
6538276 Split gate flash memory device with shrunken cell and source line array dimensions March 25, 2003
A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate
6534821 Structure with protruding source in split-gate flash March 18, 2003
A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide.
6504206 Split gate flash cell for multiple storage January 7, 2003
In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into the semiconductor substrate and
6482700 Split gate field effect transistor (FET) device with enhanced electrode registration and method November 19, 2002
Within a method for fabricating a split gate field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication there is employed a patterned mask layer as an etch mask layer for forming from a blanket floating gate electrode material layer a floating gat
6479859 Split gate flash memory with multiple self-alignments November 12, 2002
A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The
6465841 Split gate flash memory device having nitride spacer to prevent inter-poly oxide damage October 15, 2002
A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers s
6441429 Split-gate flash memory device having floating gate electrode with sharp peak August 27, 2002
A split gate electrode MOS FET device includes a tunnel oxide layer formed over a semiconductor substrate. Over the tunnel oxide layer, a doped first polysilicon layer is formed with a top surface. A native oxide which forms over the doped first polysilicon layer may have been removed as
6417049 Split gate flash cell for multiple storage July 9, 2002
In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into the semiconductor substrate and
6410957 Method of forming poly tip to improve erasing and programming speed in split gate flash June 25, 2002
A method is disclosed for forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve the erasing and programming speed of the cell. The method involves the use of an oxide other than the poly oxide that is conventionally employed in formin
6396112 Method of fabricating buried source to shrink chip size in memory array May 28, 2002
A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having
6385089 Split-gate flash cell for virtual ground architecture May 7, 2002
In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual
6380583 Method to increase coupling ratio of source to floating gate in split-gate flash April 30, 2002
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, th
6380035 Poly tip formation and self-align source process for split-gate flash cell April 30, 2002
A novel method of forming a polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notched nitride layer over the tip. At the same time, a method of forming a self-aligned source (SAS) line i
6358796 Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolati March 19, 2002
A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a "smiling" gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls
6355527 Method to increase coupling ratio of source to floating gate in split-gate flash March 12, 2002
A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed ove
6344997 Split-gate flash cell for virtual ground architecture February 5, 2002
In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual
6333228 Method to improve the control of bird's beak profile of poly in split gate flash December 25, 2001
A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing pro
6326660 Method to improve the capacity of data retention and increase the coupling ratio of source to fl December 4, 2001
A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between th
6312989 Structure with protruding source in split-gate flash November 6, 2001
A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide.
6309928 Split-gate flash cell October 30, 2001
A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F--N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over
6284596 Method of forming split-gate flash cell for salicide and self-align contact September 4, 2001
A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an
6277686 PIP capacitor for split-gate flash process August 21, 2001
A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, res
6259131 Poly tip and self aligned source for split-gate flash cell July 10, 2001
A novel method of forming a polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notched nitride layer over the tip. At the same time, a method of forming a self-aligned source (SAS) line i
6251744 Implant method to improve characteristics of high voltage isolation and high voltage breakdown June 26, 2001
A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is
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