| Patent Number |
Title Of Patent |
Date Issued |
| 6085300 |
DRAM system with simultaneous burst read and write |
July 4, 2000 |
| A DRAM system is described that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order. As a result, provided is a memory system constituted by DRAM whereby a seamless operation is assured not only for |
| 5745424 |
Method for transferring data bit for DRAM |
April 28, 1998 |
| A DRAM access system is provided which can maintain high speed as in the burst DRAM, and can perform addressing by burst transfer unit as in the synchronous DRAM, and also have high compatibility with the conventional transfer system. |
| 5732042 |
Dram array with local latches |
March 24, 1998 |
| A DRAM array has a row decoder means 2 and a column decoder 3 which are connected to a word line and a bit line of a cell matrix portion, respectively. The column decoder means 3 comprises a plurality of bit switches 44 and 46 for connecting a predetermined bit line to an output bus. |
| 5339274 |
Variable bitline precharge voltage sensing technique for DRAM structures |
August 16, 1994 |
| A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in |
| 5257232 |
Sensing circuit for semiconductor memory with limited bitline voltage swing |
October 26, 1993 |
| A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sens |
