| Patent Number |
Title Of Patent |
Date Issued |
| 7626552 |
Semiconductor device, substrate, equipment board, method for producing semiconductor device, and |
December 1, 2009 |
| A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a |
| 7579691 |
Semiconductor device, substrate, equipment board, method for producing semiconductor device, and |
August 25, 2009 |
| A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a |
| 7578676 |
Semiconductor device |
August 25, 2009 |
| A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first |
| 7554186 |
Semiconductor device |
June 30, 2009 |
| A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet dispose |
| 7400038 |
Semiconductor device, substrate, equipment board, method for producing semiconductor device, and |
July 15, 2008 |
| A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a |
| 7351068 |
Semiconductor device |
April 1, 2008 |
| A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first |
| 7027347 |
Semiconductor memory device |
April 11, 2006 |
| A semiconductor memory device for improving the utilization of a shared data bus and the data transfer rate in a multi-bank DRAM and realizing high speed data accessing without increasing a scale of a control circuit, wherein the multi-bank DRAM has memory banks provided with an addr |
| 7012831 |
Semiconductor memory device |
March 14, 2006 |
| A semiconductor memory device for realizing high speed writing while maintaining the credibility of write data, wherein a write gate is provided between a bit line and an input/output data line of a memory cell array, the write gate becomes open when a selected word line becomes an a |
| 5841688 |
Matched delay word line strap |
November 24, 1998 |
| A circuit is designed with a first lower conductor (500) having two ends. One end of the first lower conductor is coupled to a first signal source (386). A first upper conductor (544) has two ends and is spaced apart from the first lower conductor by a distance less than an allowable spa |
| 5764580 |
Semiconductor integrated circuit |
June 9, 1998 |
| A semiconductor integrated circuit capable of preventing the excessive overdriving of sense amplifiers when the supply voltage fed thereto is raised. The integrated circuit has differential amplifiers for amplifying a potential difference on complementary signal lines, and a control |
| 5293564 |
Address match scheme for DRAM redundancy scheme |
March 8, 1994 |
| An address match scheme is disclosed which allows the alternate selection of fuses blown based on either logic ones or logic zeros in an address. |
| 5257228 |
Efficiency improved DRAM row redundancy circuit |
October 26, 1993 |
| A redundancy scheme for a memory is disclosed which allows defect correction, particularly, word line to word line short correction through the use of a minimal number of redundant lines. The scheme makes use of some logical function of the non-matching address bits of two word lines |
