| Patent Number |
Title Of Patent |
Date Issued |
| 7424628 |
Serial type interface circuit, power saving method thereof, and device having serial interface |
September 9, 2008 |
| A power saving of a serial interface circuit decreases the unnecessary power consumption of a serial interface circuit, while decreasing the return time and expanding the power saving range. Gates are disposed for stopping the clock supply to a digital portion of the interface circuit |
| 7103128 |
Data synchronization circuit and communication interface circuit |
September 5, 2006 |
| There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermine |
| 6901451 |
PCI bridge over network |
May 31, 2005 |
| One embodiment of the present invention provides a method for communicating transaction request information from a PCI environment over a network. Another embodiment of the present invention provides a method for communicating request packet information from a network to a PCI enviro |
| 6877039 |
Simplified pipeline writes over a network |
April 5, 2005 |
| A system and method are provided for efficiently writing data from one bus device to another bus device across a network. Data packets to be transmitted are ordered and assigned sequence numbers and expected sequence numbers. The expected sequence number of a data packet corresponds |
| 6804673 |
Access assurance for remote memory access over network |
October 12, 2004 |
| A method and system provide access assurance regarding an RDMA transaction. The system comprises an initiating device and a target device placed across a network. The initiating device and the target device are coupled to a first and a second buses, respectively. The first and the second |
| 6799219 |
Method and apparatus for avoiding starvation in computer network |
September 28, 2004 |
| A method and apparatus for avoiding starvation at an initiator node in a computer network to which are connected at least one target node which provides service and a plurality of initiator nodes which request service from the target node. The method includes: when a request is received |
| 6732212 |
Launch raw packet on remote interrupt |
May 4, 2004 |
| One embodiment of the present invention provides a method for processing a remote interrupt signal or a remote event. Another embodiment of the present invention provides a system for issuing a raw packet over a network in response to a remote interrupt or a remote event. Another emb |
| 6684281 |
Fast delivery of interrupt message over network |
January 27, 2004 |
| A computer network system and a method for fast delivery of an interrupt message over a computer network enables a first processor coupled to the computer network to very quickly send an interrupt message to a second processor coupled to the computer network, by directly writing the |
| 6678758 |
Dynamic queuing for read/write requests |
January 13, 2004 |
| A PCI (peripheral component interconnect) network adaptor manages read/write requests through the establishment of dynamic queues. The PCI network adaptor establishes a unique queue for each destination node that enables the requests for each node to be processed separately. The PCI |
| 6092173 |
Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data tra |
July 18, 2000 |
| A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The dire |
| 6038674 |
Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data tra |
March 14, 2000 |
| A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The dire |
| 5890217 |
Coherence apparatus for cache of multiprocessor |
March 30, 1999 |
| A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system |
| 5761728 |
Asynchronous access system controlling processing modules making requests to a shared system mem |
June 2, 1998 |
| An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a |
| 5737573 |
Asynchronous access system having an internal buffer control circuit which invalidates an intern |
April 7, 1998 |
| An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second |
| 5734845 |
Bus arbiter provided in a multi-processor system |
March 31, 1998 |
| In a multi-processor system in which a plurality of units such as a CPU serving as an information processing unit and an I/O control unit can be connected over a system bus, when the plurality of units issue use requests for the system bus, a bus arbiter grants a use authority for the |
| 5727151 |
Message control system specifying message storage buffer for data communication system with gene |
March 10, 1998 |
| A message control system is for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In this message control system, a memory u |
| 5708795 |
Asynchronous access system for multiprocessor system and processor module used in the asynchrono |
January 13, 1998 |
| In an asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and at least one shared memory module connected to the system bus, each of the processor modules includes a processor and an internal buffer. The processor write |
| 5704056 |
Cache-data transfer system |
December 30, 1997 |
| The present invention provides a cache-data transfer system improving a cache-hit rate by making a block size of the external cache memory longer than the block size of an internal cache memory. The system makes a block size of the external cache memory longer than a block size of the in |
| 5634037 |
Multiprocessor system having a shared memory with exclusive access for a requesting processor wh |
May 27, 1997 |
| An exclusive control system is provided in a system having a memory module and a plurality of processing modules sharing the memory module, each of the plurality of processing modules exclusively accessing the memory module while prohibiting other processing modules from accessing the |
| 5592624 |
Data communication for controlling message transmission and reception among processing modules u |
January 7, 1997 |
| A message control system for a data communication system in the form of a loosely coupled multiprocessing system, in which a plurality of processing modules having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit, within each process |
| 5500945 |
Apparatus and method for controlling a system bus of a multiprocessor system |
March 19, 1996 |
| In a bus arbiter connected to a system bus of a multi-processor system having a plurality of modules respectively having processors, a first unit detects an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferr |
| 5428768 |
System for checking comparison check function of information processing apparatus |
June 27, 1995 |
| A check system for checking a comparison check function of an information processing apparatus which includes first and second microprocessors includes a check part for supplying mutually different data to the first and second microprocessors when checking the comparison check function, |
| 5402421 |
Bus control device and bus control method |
March 28, 1995 |
| When a unit connected to a data transfer bus on which data transfer is controlled synchronously with a bus cycle makes a request for using the bus, permission is granted to one of the units which have made the request. The permission to use the bus is switched over at a bus cycle whe |
