| Patent Number |
Title Of Patent |
Date Issued |
| 7563671 |
Method for forming trench capacitor and memory cell |
July 21, 2009 |
| A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the |
| 7554148 |
Pick-up structure for DRAM capacitors |
June 30, 2009 |
| A pick-up structure for DRAM capacitors and a DRAM process are described. A substrate with trenches therein is provided, wherein the trenches include a first trench and the sidewall of each of the trenches is formed with a dielectric layer thereon. A conductive layer is formed on the |
| 7541634 |
Trench capacitor |
June 2, 2009 |
| A trench capacitor including a substrate, at least a group of capacitor units, an isolation structure and a conductive layer is described. The substrate includes a first trench and a second trench. The group of capacitor units is disposed in the substrate. The group of capacitor unit |
| 7494890 |
Trench capacitor and method for manufacturing the same |
February 24, 2009 |
| A structure of a trench capacitor and method for manufacturing the same. The method includes providing a substrate having a defined memory area and logic area, and performing an STI process to form at least one STI region on the memory area of the substrate and at least one STI region on |
| 7407852 |
Trench capacitor of a DRAM and fabricating method thereof |
August 5, 2008 |
| A method of fabricating trench capacitors is described. A substrate having at least one isolation structure is provided. A first trench and a second trench are formed in the substrate beside the isolation structure. A first lower electrode and a second lower electrode are formed in the |
| 7351634 |
Trench-capacitor DRAM device and manufacture method thereof |
April 1, 2008 |
| A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are |
| 7335553 |
Method for forming trench capacitor and memory cell |
February 26, 2008 |
| A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the |
| 7271056 |
Method of fabricating a trench capacitor DRAM device |
September 18, 2007 |
| The present invention discloses a STI-first process for making trench DRAM devices. According to the preferred embodiment, the etching recipe for etching the STI region in the memory array is completely compatible with the logic STI process. |
