| Patent Number |
Title Of Patent |
Date Issued |
| 8138036 |
Through silicon via and method of fabricating same |
March 20, 2012 |
| A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide |
| 8004289 |
Wafer-to-wafer alignments |
August 23, 2011 |
| Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semic |
| 7898063 |
Through substrate annular via including plug filler |
March 1, 2011 |
| A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively |
| 7851923 |
Low resistance and inductance backside through vias and methods of fabricating same |
December 14, 2010 |
| A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in |
| 7741722 |
Through-wafer vias |
June 22, 2010 |
| A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure |
| 7678696 |
Method of making through wafer vias |
March 16, 2010 |
| A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon |
| 7563714 |
Low resistance and inductance backside through vias and methods of fabricating same |
July 21, 2009 |
| A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in |
| 7557597 |
Stacked chip security |
July 7, 2009 |
| The present invention is directed to an integrated circuit module device. The device includes a first semiconductor chip having a first circuit layer and at least one first interconnection element disposed on a first chip surface. The at least one first interconnection element is ele |
| 7474104 |
Wafer-to-wafer alignments |
January 6, 2009 |
| Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semic |
| 7348210 |
Post bump passivation for soft error protection |
March 25, 2008 |
| A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the |
| 7276787 |
Silicon chip carrier with conductive through-vias and method for fabricating same |
October 2, 2007 |
| A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value whi |
| 7193423 |
Wafer-to-wafer alignments |
March 20, 2007 |
| Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semic |
| 6642080 |
Chip-on-chip interconnections of varied characterstics |
November 4, 2003 |
| Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same |
| 6507115 |
Multi-chip integrated circuit module |
January 14, 2003 |
| A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are con |
| 6294406 |
Highly integrated chip-on-chip packaging |
September 25, 2001 |
| The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry. |
| 6225699 |
Chip-on-chip interconnections of varied characteristics |
May 1, 2001 |
| Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same |
| 5977640 |
Highly integrated chip-on-chip packaging |
November 2, 1999 |
| The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry. |
| 5935763 |
Self-aligned pattern over a reflective layer |
August 10, 1999 |
| An opening in an insulator on a substrate is self-aligned to a reflective region on the substrate. The opening is formed by shining blanket radiation on photoresist on the insulator and developing to open the resist and insulator. The resist region that is above the reflective region |
| 5923181 |
Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chi |
July 13, 1999 |
| Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surfac |
| 5686843 |
Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chi |
November 11, 1997 |
| Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surfac |
