| Patent Number |
Title Of Patent |
Date Issued |
| 7599489 |
Accelerating cryptographic hash computations |
October 6, 2009 |
| Provided is an apparatus and method for accelerating cryptographic hash computations. For example, in a cryptographic hash computation such as SHA-1, multiple execution units in a processor can process loosely coupled data. Specifically, after preprocessing a message with a particula |
| 7543112 |
Efficient on-chip instruction and data caching for chip multiprocessors |
June 2, 2009 |
| The storage of data line in one or more L1 caches and/or a shared L2 cache of a chip multiprocessor is dynamically optimized based on the sharing of the data line. In one embodiment, an enhanced L2 cache directory entry associated with the data line is generated in an L2 cache directory |
| 7529911 |
Hardware-based technique for improving the effectiveness of prefetching during scout mode |
May 5, 2009 |
| One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. Upon encountering a non-data dependent stall condition, the system performs a checkpoint and commences execution of instructions in |
| 7480787 |
Method and structure for pipelining of SIMD conditional moves |
January 20, 2009 |
| A mask is first generated in a general-purpose integer register. The mask is generated by executing a single instruction multiple data (SIMD) instruction on a plurality of operands stored in a plurality of registers and by writing the result to the general-purpose integer register. Next, |
| 7434031 |
Execution displacement read-write alias prediction |
October 7, 2008 |
| RAW aliasing can be predicted with register bypassing based at least in part on execution displacement alias prediction. Repeated aliasing between read and write operations (e.g., within a loop), can be reliably predicted based on displacement between the aliasing operations. Perform |
| 7434004 |
Prefetch prediction |
October 7, 2008 |
| Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution mechanisms. Read operations that most likely trigger runahead execution are identified. |
| 7373482 |
Software-based technique for improving the effectiveness of prefetching during scout mode |
May 13, 2008 |
| One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. During operation, the system executes program instructions in a normal-execution mode. Upon encountering a condition which causes the |
| 7013377 |
Method and apparatus for alleviating register window size constraints |
March 14, 2006 |
| A method and apparatus provides the capability for a single function to safely use multiple register windows within the same function, with minimal additional support from the operating system, by specifying a new window pointer, the "Effective Current Window Pointer" (ECWP), to be used |
