| Patent Number |
Title Of Patent |
Date Issued |
| 7035981 |
Asynchronous input/output cache having reduced latency |
April 25, 2006 |
| The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address |
| 6823439 |
Message logging |
November 23, 2004 |
| A method includes storing a plurality of system status messages of a specified size, and transmitting the status messages as a combined status message of a size larger than said specified size to an external device. In one aspect, the system status messages may have sizes that are less |
| 6772295 |
System and method for managing data in an I/O cache |
August 3, 2004 |
| The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; na |
| 6542968 |
System and method for managing data in an I/O cache |
April 1, 2003 |
| The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; na |
| 6457105 |
System and method for managing data in an asynchronous I/O cache memory |
September 24, 2002 |
| The present invention is generally directed to a system and method for providing improved memory management in an asynchronous I/O cache memory. The method includes the steps of identifying a request for data from the system memory by a requesting device that is in communication with the |
| 6311247 |
System for bridging a system bus with multiple PCI buses |
October 30, 2001 |
| The present invention is directed to a system for interfacing a system bus to a plurality of Peripheral Component Interconnect (PCI) buses. Specifically, the invention is directed to a system that interfaces a system bus to a plurality of PCI buses, wherein each PCI bus is dedicated |
| 6295582 |
System and method for managing data in an asynchronous I/O cache memory to maintain a predetermi |
September 25, 2001 |
| A system and method are described for providing improved cache memory management. Broadly, the system and method improve the performance of an asynchronous input/output (I/O) cache by ensuring that a certain predetermined amount of space is readily available, at all times, to receive |
| 6279081 |
System and method for performing memory fetches for an ATM card |
August 21, 2001 |
| The present invention is generally directed to a system and method for fetching data from a system memory to an ATM card. The method includes the steps of receiving a request (via a PCI bus) to fetch data from memory, and identifying the request as an ATM request. The method then determi |
| 6157977 |
Bus bridge and method for ordering read and write operations in a write posting system |
December 5, 2000 |
| A bus bridge is disclosed that provides an interface between two computer buses and guarantees the proper ordering of write operations mastered from one bus relative to read operations mastered from the other bus where the presence of write posting storage in the bus bridge could cause o |
| 6108721 |
Method and apparatus for ensuring data consistency between an i/o channel and a processor |
August 22, 2000 |
| In a method and apparatus that ensures data consistency between an I/O channel and a processor, system software issues an instruction which causes the issuance of a transaction when notification of a DMA completion is received. The transaction instructs the I/O channel to enforce coh |
| 5687395 |
Main memory buffer for low cost / high performance input/output of data in a computer system |
November 11, 1997 |
| A system for transferring data between main memory and an input/output device in a computer system, where device driver software stores an address of a circular buffer into the device and then the device automatically transfers data to or from the buffer. The system reduces complexit |
| 5557756 |
Chained arbitration |
September 17, 1996 |
| A bus arbitration circuit, having a state machine which receives a processor request signal, a request signal from each of a group of internal input/output devices, and an external device request signal. The state machine sends a processor grant signal, a grant signal to one of the i |
