| Patent Number |
Title Of Patent |
Date Issued |
| 6195745 |
Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental inte |
February 27, 2001 |
| The existing execution units of a high-performance processor are augmented by tile addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small |
| 5923579 |
Optimized binary adder and comparator having an implicit constant for an input |
July 13, 1999 |
| A three-input comparator, where one of the inputs is an implicit constant, is formed with a special carry-save adder (CSA) followed by carry propagation circuitry. The special CSA uses two different bit cells depending upon whether that bit position in the constant input is a one or |
| 5919256 |
Operand cache addressed by the instruction address for reducing latency of read instruction |
July 6, 1999 |
| A structure for, and a method of operating, an operand cache to store operands retrieved from a memory. An instruction requiring an operand stored in the memory, is allowed to speculatively execute in an execution unit of a processor using an operand stored in an entry (corresponding to |
| 5822786 |
Apparatus and method for determining if an operand lies within an expand up or expand down segme |
October 13, 1998 |
| Dedicated parallel comparators perform expand up or expand down segment limit checks for memory accesses. A first three-input comparator has as inputs the complement of the segment limit, the effective address of the first byte of the access, and an configurable third input. For expand u |
| 5802339 |
Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental inte |
September 1, 1998 |
| The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small i |
| 5699279 |
Optimized binary adders and comparators for inputs having different widths |
December 16, 1997 |
| A first two-input adder computes the sum of one wider and one narrower input by combining a conventional adder for the low-order bits with an incrementer and selection logic for the high-order bits. A second three-input adder computes the sum of one wider and two narrower inputs in a |
| 5675758 |
Processor having primary integer execution unit and supplemental integer execution unit for perf |
October 7, 1997 |
| The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small i |
| 5590351 |
Superscalar execution unit for sequential instruction pointer updates and segment limit checks |
December 31, 1996 |
| An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the |
| 5517440 |
Optimized binary adders and comparators for inputs having different widths |
May 14, 1996 |
| A first two-input adder computes the sum of one wider and one narrower input by combining a conventional adder for the low-order bits with an incrementer and selection logic for the high-order bits. A second three-input adder computes the sum of one wider and two narrower inputs in a |
| 5418736 |
Optimized binary adders and comparators for inputs having different widths |
May 23, 1995 |
| A first two-input adder computes the sum of one wider and one narrower input by combining a conventional adder for the low-order bits with an incrementer and selection logic for the high-order bits. A second three-input adder computes the sum of one wider and two narrower inputs in a |
| 5394351 |
Optimized binary adder and comparator having an implicit constant for an input |
February 28, 1995 |
| A three-input comparator, where one of the inputs is an implicit constant, is formed with a special carry-save adder (CSA) followed by carry propagation circuitry. The special CSA uses two different bit cells depending upon whether that bit position in the constant input is a one or |
