Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Sonnier; David P.
Address:
Austin, TX
No. of patents:
43
Patents:












Patent Number Title Of Patent Date Issued
8255644 Network communications processor architecture with memory load balancing August 28, 2012
Described embodiments provide a memory system including a plurality of addressable memory arrays. Data in the arrays is accessed by receiving a logical address of data in the addressable memory array and computing a hash value based on at least a part of the logical address. One of the
8214868 Flexible traffic management and shaping processing for multimedia distribution July 3, 2012
Apparatus for distributing streaming multimedia to at least one end client over a network includes memory and at least one processor operatively connected to the memory. The processor is operative: (i) to receive the streaming multimedia from at least one multimedia source via at lea
7930691 Methods and apparatus for updating data structures during in-service upgrade of software in netw April 19, 2011
Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of managing data structures associated with code executable on a packet processor includes the following steps. Data structure
7912069 Virtual segmentation system and method of operation thereof March 22, 2011
A virtual segmentation system and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to (i) receive at least a portion of a protocol data unit and (ii) store the at least a portion of the protocol
7802245 Methods and apparatus for performing in-service upgrade of software in network processor September 21, 2010
Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of performing an in-service upgrade of code, storable in a memory associated with a packet processor and executable on the pac
7801164 Two dimensional timeout table mechanism with optimized delay characteristics September 21, 2010
Improved timeout table mechanism are disclosed. By way of example, a method for providing timeout delays for data queues in a processing system includes the following steps. A timeout structure is maintained. The timeout structure includes two or more groups, each group including two
7729387 Methods and apparatus for controlling latency variation in a packet transfer network June 1, 2010
Methods and apparatus for controlling latency variation of packets received in a packet transfer network are provided. A plurality of packets is received at a network element of a receive node of the packet transfer network. A time-stamp is provided for each of the plurality of packe
7558892 Processing device peripheral with integral network interface circuitry July 7, 2009
A peripheral connectable to a processing device includes a housing and network interface circuitry at least partially enclosed within the housing, the network interface circuitry being utilizable by the processing device to establish a connection between the processing device and a n
7542425 Traffic management using in-band flow control and multiple-rate traffic shaping June 2, 2009
Backpressure information is communicated from a physical layer device to a link layer device in a communication system by generating a flow control message in the physical layer device responsive to a detected condition relating to at least a given one of a plurality of queues of the phy
7480821 Method for encoding/decoding a binary signal state in a fault tolerant environment January 20, 2009
A method for use in a fault tolerant environment for assuring that devices within the environment switch between primary and back-up systems in response to remotely generated control signals. In one embodiment, the inventive system uses a binary code in the form of a pair of different
7477636 Processor with scheduler architecture supporting multiple distinct scheduling algorithms January 13, 2009
A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of
7443793 Processor with dynamic table-based scheduling using linked transmission elements for handling tr October 28, 2008
A processor includes scheduling circuitry for scheduling data blocks for transmission from multiple transmission elements, and traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks
7424027 Head of line blockage avoidance system and method of operation thereof September 9, 2008
A head of line blockage avoidance system for use with network systems that employ packets having an associated priority and a method of operation thereof. In one embodiment, the head of line blockage avoidance system includes: (1) m inputs, m numbering at least two, configured to receive
7313089 Method and apparatus for switching between active and standby switch fabrics with no loss of dat December 25, 2007
A switching system for a data traffic network. A plurality of line cards provide input and output connections to a plurality of data lines and further are connected to at least two switch fabrics, one of which is designated the active switch fabric and the other designated the standby
7275117 Fast pattern processor including a function interface system September 25, 2007
A fast pattern processor having an internal function bus and an external function bus. In one embodiment, a fast pattern processor includes: (1) an internal function bus, (2) an external function bus, (3) a context memory having a block buffer and a argument signature register wherein
7245624 Processor with table-based scheduling using software-controlled interval computation July 17, 2007
A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data
7224681 Processor with dynamic table-based scheduling using multi-entry table locations for handling tra May 29, 2007
A processor includes scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements. The scheduling circuitry has at least one time slot table accessible thereto, and is configured for utilization of the time slot table in scheduling the data
7215675 Processor with software-controlled programmable service levels May 8, 2007
A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by
7206880 Multi-protocol bus system and method of operation thereof April 17, 2007
A multi-protocol bus system and a method of operating the same. In one embodiment, the multi-protocol bus system includes a plurality of protocol indicators associated with an address space, each of the plurality of protocol indicators associated with a segment of the address space a
7159219 Method and apparatus for providing multiple data class differentiation with priorities using a s January 2, 2007
A scheduler for shared network resources implementing a plurality of user selectable data scheduling schemes within a single hardware device. The schemes include strict priority, priority for one class plus smooth deficit weighted round robin for the other classes, bandwidth limited
7149211 Virtual reassembly system and method of operation thereof December 12, 2006
A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at
7116680 Processor architecture and a method of processing October 3, 2006
A process and architecture to simplify the implementation of a high-speed scheduler. A traditional packet based scheduler works the length of the packet. Instead, the present invention uses a transmit queue that determines how many times a portion of a packet needs to be transmitted
7111289 Method for implementing dual link list structure to enable fast link-list pointer updates September 19, 2006
A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists a
7075936 Voice packet processor and method of operation thereof July 11, 2006
A voice packet processor for use with voice applications employing a fast pattern processor (FPP) and a routing switch processor (RSP) that receive and transmit protocol data units (PDUs) and a method of operation thereof. In one embodiment, the voice packet processor includes (1) a
7009979 Virtual segmentation system and method of operation thereof March 7, 2006
A virtual segmentation system for use with a routing switch processor and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to receive at least a portion of a protocol data unit and assemble
7000034 Function interface system and method of processing issued functions between co-processors February 14, 2006
A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an iss
6925514 Multi-protocol bus system and method of operation thereof August 2, 2005
A multi-protocol bus system and a method of operating the same. In one embodiment, the multi-protocol bus system includes a plurality of protocol indicators associated with an address space, each of the plurality of protocol indicators associated with a segment of the address space and
6850516 Virtual reassembly system and method of operation thereof February 1, 2005
A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at l
6801991 Method and apparatus for buffer partitioning without loss of data October 5, 2004
An apparatus and method for moving and/or resizing logical buffers that comprise a memory space without the loss of data. Each buffer comprises a linear and contiguous set of storage locations, and operates according to a FIFO priority scheme, using a read address pointer to indicate the
6754795 Methods and apparatus for forming linked list queue using chunk-based structure June 22, 2004
A processing system comprises processing circuitry and memory circuitry coupled to the processing circuitry. The memory circuitry is configurable to maintain at least one queue structure representing a list of data units (e.g., pointers to packets stored in a packet memory). The queue st
6687803 Processor architecture and a method of processing February 3, 2004
A processor architecture including a processor and local memory arrangement where the local memory may be accessed by the processor and other resources at substantially the same time. As a result, the processor may initiate a new or current process following a previous process without
6668313 Memory system for increased bandwidth December 23, 2003
A system and method for memory management in a high-speed network environment. Multiple packets are interleaved in data streams and sent to a Memory Manager System. Read and write requests are queued in FIFO buffers. Subsets of these requests are grouped and ordered to optimize proce
6631131 Transpose table biased arbitration scheme October 7, 2003
A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requestors. The rows of the table are fetched to assure that requestors having high bias
6151689 Detecting and isolating errors occurring in data communication in a multiple processor system November 21, 2000
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU
6145061 Method of management of a circular queue for asynchronous access November 7, 2000
A circular queue is asynchronously accessed and managed by two separate processing elements. Each data element is added to the queue together with a zero data element that both marks the tail of the queue and signifies that the queue is empty. Data elements are removed from the queue in
5983269 Method and apparatus for configuring routing paths of a network communicatively interconnecting November 9, 1999
A multiple processing system, comprises at least a pair of processor units communicatively connected to a number of peripheral devices through a network that includes routing devices interconnected to route information in the form of message packets sent between the processor units and
5964835 Storage access validation to data messages using partial storage address data indexed entries co October 12, 1999
A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination o
5751932 Fail-fast, fail-functional, fault-tolerant multiprocessor system May 12, 1998
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU
5710549 Routing arbitration for shared resources January 20, 1998
A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for providing two levels of arbitration to select one of the inputs for data communication to an output. The first (lower) l
5694121 Latency reduction and routing arbitration for network message routers December 2, 1997
A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for selecting one of the inputs based upon a comparison of accumulated bias values that can change over time when an input i
5682528 Spoon-feed initialization in a multiprocessor system October 28, 1997
The present invention provides a mechanism for initial execution of software code by a processor in a multiprocessor system. In the preferred embodiment, the multiprocessor system has registers implemented at a reset vector location in a processor. The registers are first loaded with a
5574849 Synchronized data transmission between elements of a processing system November 12, 1996
Two identical streams of multi-bit symbols are received by a pair of storage elements, each having multiple locations and first and second pointer counters respectively identifying the locations at which received symbols are stored and from which stored symbols are retrieved. The sto
5548463 System for switching power and scrubbing power mixing devices for faults August 20, 1996
A power switching circuit module includes two power rails coupling independent power supplies to the input of a DC controller and test circuits to detect latent faults in power mixing devices included in the circuit.










 
 
  Recently Added Patents
Ionization device, mass spectrometer including the ionization device, and image generation system including the ionization device
Kit and method for the capture of tumor cells
Security patch update processor
Thiocyanato or isothiocyanato substituted naphthalene diimide and rylene diimide compounds and their use as n-type semiconductors
Method of inspecting wafer
Charge pump circuit and power-supply method for dynamically adjusting output voltage
Tray for microwave cooking and folding of a food product
  Randomly Featured Patents
Virtual machine system
Hammock structure
Sales promotion system supporting a plurality of differing sellers
Arrangement for cleaning contaminated ground water
Piezoelectric element, liquid ejecting head, and liquid ejecting apparatus
Pneumatic tire including blocks having reinforcing portions
Optical temperature measurement techniques
Reel brake assembly actuated by linear stepper motor
Flooring system with a plurality of different decorative upper surfaces
Belt for continuously variable transmission