| Patent Number |
Title Of Patent |
Date Issued |
| 7553742 |
Method(s) of forming a thin layer |
June 30, 2009 |
| A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insul |
| 7537980 |
Method of manufacturing a stacked semiconductor device |
May 26, 2009 |
| In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern having a first opening may be formed on the seed layer. A first SEG process may be carried out to form a first plug partially fillin |
| 7422965 |
Methods of fabricating p-type transistors including germanium channel regions |
September 9, 2008 |
| A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-c |
| 7396761 |
Semiconductor device and method of manufacturing the same |
July 8, 2008 |
| In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is |
| 7364990 |
Epitaxial crystal growth process in the manufacturing of a semiconductor device |
April 29, 2008 |
| First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection stru |
