| Patent Number |
Title Of Patent |
Date Issued |
| 7609089 |
FPGA architecture at conventional and submicron scales |
October 27, 2009 |
| Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable imp |
| 7544977 |
Mixed-scale electronic interface |
June 9, 2009 |
| Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and |
| 7530032 |
Nanowire crossbar implementations of logic gates using configurable, tunneling resistor junction |
May 5, 2009 |
| Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a nanowire crossbar comprises two or more layers of approximately p |
| 7525833 |
Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers |
April 28, 2009 |
| One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires of the logic circuit. In a described embodiment, the nanoscale shift register includes two |
| 7517794 |
Method for fabricating nanoscale features |
April 14, 2009 |
| One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon layer exposed at t |
| 7444495 |
Processor and programmable logic computing arrangement |
October 28, 2008 |
| A computing arrangement including a processor and programmable logic. In various embodiments, the arrangement includes an instruction processing circuit coupled to a programmable logic circuit, and a memory arrangement coupled to the instruction processing circuit and to the programmable |
| 7436209 |
Nanoscale electronic latch |
October 14, 2008 |
| In one embodiment of the present invention, a nanoscale latch is implemented by interconnecting an enable line, two control lines, and a pull-down line, when needed, to a signal line carrying encoded binary values to be latched and subsequently output. The enable line is interconnect |
| 7405462 |
FPGA architecture at conventional and submicron scales |
July 29, 2008 |
| Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable imp |
| 7358614 |
Antisymmetric nanowire crossbars |
April 15, 2008 |
| Various embodiments of the present invention are directed to antisymmetric nanowire-crossbar-circuit designs. Antisymmetric nanowire crossbars are composed, in certain embodiments of the present invention, of two or more microregions that receive input signals and two or more microregion |
| 7319416 |
Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays |
January 15, 2008 |
| Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the prese |
| 7307448 |
Interconnectable nanoscale computational stages |
December 11, 2007 |
| Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the confi |
| 7292498 |
Factored nanoscale multiplexer/demultiplexer circuit for interfacing nanowires with microscale a |
November 6, 2007 |
| Embodiments of the present invention are related to nanoscale multiplexers and demultiplexers that employ randomly fabricated interconnections between nanowire signal lines and microscale or sub-microscale address lines. A greater number of address lines than a minimal number of address |
| 7257016 |
Enhanced nanowire-crossbar latch array |
August 14, 2007 |
| Various embodiments of the present invention are directed to a signal-storing nanowire-crossbar latch array. In one embodiment, the signal-storing nanowire-crossbar latch array is fabricated from three signal lines, including an enable line and two control lines, that cross and inter |
| 7254799 |
Method for allocating resources in heterogeneous nanowire crossbars having defective nanowire ju |
August 7, 2007 |
| Various embodiments of the present invention provide methods for allocating nanowire junctions in a nanowire crossbar having one or more randomly distributed non-functional crossbar nanowire junctions. In certain embodiments, the method constructs a circuit graph based on the circuit |
| 7248592 |
Partitionable data fabric and computing arrangement |
July 24, 2007 |
| A circuit arrangement and method for interfacing a node and a data fabric. In a computing arrangement that includes a plurality of nodes intercoupled by the data fabric, each node is assigned to one of a plurality of partitions. A node-interface circuit is configured to interface wit |
| 7242215 |
Nanoscale latches and impedance-encoded logic for use in nanoscale state machines, nanoscale pip |
July 10, 2007 |
| Various embodiments of the present invention are directed to implementation and use of logic-state-storing, impedance-encoded nanoscale, impedance-encoded latches that store logic values as impedance states within nanoscale electronic circuits that employ impedance-driven logic. In c |
| 7228518 |
Method for reducing the size and nanowire length used in nanowire crossbars without reducing the |
June 5, 2007 |
| Various embodiments of the present invention provide methods for designing multilayer nanowire crossbars that are functionally equivalent to two-layer nanowire-crossbar designs. Given a two-layer nanowire-crossbar design having two or more columns of microregions, in certain embodime |
| 7227379 |
Nanoscale latch-array processing engines |
June 5, 2007 |
| One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch |
| 7159195 |
Reduction of storage elements in synthesized synchronous circuits |
January 2, 2007 |
| Method and apparatus for reducing a number of storage elements in a synthesized synchronous circuit. In one embodiment, the circuit is represented as a directed, partitioned graph. The graph is divided into a plurality of time-ordered timeslots that are bounded by storage elements. T |
| 6988192 |
Method and apparatus for compiling source code to configure hardware |
January 17, 2006 |
| An embodiment of the invention includes, parsing a source code, performing a plurality of optimizations on the parsed code, generating a plurality of configuration instruction sets based on the optimized source code and automatically selecting one of the plurality of generated configurat |
| 6968275 |
Pipelined digital circuit for determining the conformational energy of a folded protein |
November 22, 2005 |
| The present invention provides a method and apparatus to significantly accelerate the searching process based on the Monte Carlo principle and the lattice model. Specifically, the energy status of a lattice-based protein conformation is evaluated by modeling the folding process through |
| 6952358 |
Molecular wire content addressable memory |
October 4, 2005 |
| In one embodiment, a content addressable memory (CAM), includes: a word line driver configured to provide a driving signal; a tag memory including M word lines traversing through the tag memory and intersecting with 2N bit lines, where M and N are each suitable integer values, where each |
| 6941541 |
Efficient pipelining of synthesized synchronous circuits |
September 6, 2005 |
| Method and apparatus for generating a pipelined synchronized circuit representation of a program loop. A dependence graph is generated from the program loop. The dependence graph represents operations and registers and connections therebetween. A minimum clock period and initiation inter |
| 6771402 |
Method and apparatus for generating a hologram |
August 3, 2004 |
| A method and system for generating a hologram include a computer (104) connected to a printer (108). A mathematical description (102) of an object, including for example the physical dimensions of the object, is provided to the computer (104). The computer (104) computes a holographic |
| 6704909 |
Reduction of storage elements in synthesized synchronous circuits |
March 9, 2004 |
| Method and apparatus for reducing a number of storage elements in a synthesized synchronous circuit. In one embodiment, the circuit is represented as a directed, partitioned graph. The graph is divided into a plurality of time-ordered time slots that are bounded by storage elements. |
| 6128773 |
Automatically measuring software complexity |
October 3, 2000 |
| The inventive metric tool estimates the entropy of the source code as a measure of the complexity of the software. The tool considers the dependency of the symbols in the software. The tool constructs a data graph representing the structure of the program. Each symbol is shown as a n |
| 5991893 |
Virtually reliable shared memory |
November 23, 1999 |
| The inventive computer system uses a layer of software between the operating system and the hardware that localizes the fail-safe protocols into a single module. The system also uses shared memory allocation functions as the interface with the operating system. The memory allocation |
| 5729752 |
Network connection scheme |
March 17, 1998 |
| A network connection scheme for a direct or an indirect network. The network is implemented in two levels of circuit boards. Every board in the first level crosses all the boards in the second level, with every processor in the first level circuit board coupled to at least two proces |
| 5519629 |
Tileable gate array cell for programmable logic devices and gate array having tiled gate array c |
May 21, 1996 |
| A logic and routing cell for constructing a programmable gate array. The gate array may be constructed by tiling a wafer surface with this single logic and routing cell design. The logic and routing cell includes both the logic cell and the routing circuitry needed to connect that logic |
| 5315178 |
IC which can be used as a programmable logic cell array or as a register file |
May 24, 1994 |
| A programmable logic cell array (PLCA) architecture that provides efficient support for demultiplexers or multi-ported register files without sacrificing PLCA functionality or flexibility is disclosed. The architecture of conventional PLCs is modified so that demultiplexers can be im |
