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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Smythe; John
Address:
Boise, ID
No. of patents:
32
Patents:












Patent Number Title Of Patent Date Issued
8298964 Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticle October 30, 2012
A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the
8283203 Methods utilizing microwave radiation during formation of semiconductor constructions October 9, 2012
Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a
8282999 Spin-on film processing using acoustic radiation pressure October 9, 2012
An apparatus and process operate to impose sonic pressure upon a spin-on film liquid mass that exhibits a liquid topography and in a solvent vapor overpressure to alter the liquid topography. Other apparatus and processes are disclosed.
8236372 Methods of forming capacitors having dielectric regions that include multiple metal oxide-compri August 7, 2012
Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrod
8223539 GCIB-treated resistive device July 17, 2012
The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a low
8211803 Spacer process for on pitch contacts and related structures July 3, 2012
Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects
8211743 Methods of forming non-volatile memory cells having multi-resistive state material between condu July 3, 2012
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally ou
8203179 Device having complex oxide nanodots June 19, 2012
Devices are disclosed, such as those having a memory cell. The memory cell includes an active area formed of a semiconductor material; a first dielectric over the semiconductor material; a second dielectric comprising a material having a perovskite structure over the first dielectric
8198124 Methods of self-aligned growth of chalcogenide memory access device June 12, 2012
Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrod
8193607 Memory cell having GeN-containing material and variable resistance material embedded within insu June 5, 2012
A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater materi
8133664 Methods of forming patterns March 13, 2012
Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the
8120184 Semiconductor constructions and methods of forming layers February 21, 2012
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and v
8114468 Methods of forming a non-volatile resistive oxide memory array February 14, 2012
A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of
8048755 Resistive memory and methods of processing resistive memory November 1, 2011
Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, formi
8043975 Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors October 25, 2011
Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing
8034655 Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and metho October 11, 2011
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode.
8034315 Methods of forming devices comprising carbon nanotubes October 11, 2011
Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is directly over the CNTs, with t
7985617 Methods utilizing microwave radiation during formation of semiconductor constructions July 26, 2011
Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a
7952174 Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticle May 31, 2011
A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the
7939442 Strontium ruthenium oxide interface May 10, 2011
Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium
7927975 Semiconductor material manufacture April 19, 2011
Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.
7902084 Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors March 8, 2011
Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing
7892964 Vapor deposition methods for forming a metal-containing layer on a substrate February 22, 2011
Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), wh
7851307 Method of forming complex oxide nanodots for a charge trap December 14, 2010
Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source ma
7785978 Method of forming memory cell using gas cluster ion beams August 31, 2010
A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater materi
7737559 Semiconductor constructions June 15, 2010
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and v
7737039 Spacer process for on pitch contacts and related structures June 15, 2010
Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects
7709345 Trench isolation implantation May 4, 2010
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of e
7557047 Method of forming a layer of material using an atomic layer deposition process July 7, 2009
Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative embodiment, the method includes identifying a target characteristic for the layer of material, determining a precursor pulse
7439157 Isolation trenches for memory devices October 21, 2008
A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a d
7273796 Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fa September 25, 2007
A method of fabricating integrated circuitry includes depositing a spin-on-dielectric over a semiconductor substrate. The spin-on-dielectric comprises a polysilazane. Only some of the polysilazane is etched from the semiconductor substrate. Such etching comprises exposure to an etchi
7262135 Methods of forming layers August 28, 2007
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and v










 
 
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