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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Smith; Taber H.
Address:
Fremont, CA
No. of patents:
10
Patents:




Patent Number Title Of Patent Date Issued
7393755 Dummy fill for integrated circuits July 1, 2008
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ
7383521 Characterization and reduction of variation for integrated circuits June 3, 2008
A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circu
7380220 Dummy fill for integrated circuits May 27, 2008
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ
7363598 Dummy fill for integrated circuits April 22, 2008
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ
7363099 Integrated circuit metrology April 22, 2008
Sites to be measured on a device that is to be fabricated using at least one fabrication process, are selected based on a pattern-dependent model of the process. A metrology tool to measure a parameter of a semiconductor device includes a control element to select sites for measureme
7360179 Use of models in integrated circuit fabrication April 15, 2008
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ
7356783 Dummy fill for integrated circuits April 8, 2008
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ
7174520 Characterization and verification for integrated circuit designs February 6, 2007
Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variati
7152215 Dummy fill for integrated circuits December 19, 2006
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ
7124386 Dummy fill for integrated circuits October 17, 2006
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The describ


 
 
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