| Patent Number |
Title Of Patent |
Date Issued |
| 6475846 |
Method of making floating-gate memory-cell array with digital logic transistors |
November 5, 2002 |
| A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvo |
| 6246102 |
Integrated circuits, transistors, data processing systems, printed wiring boards, digital comput |
June 12, 2001 |
| An integrated circuit includes conductive elements and a radiation sensitive material interposed between the conductive elements and dosed to different conductivities in different portions thereof. Another aspect is a process of integrated circuit fabrication including steps of depositin |
| 6060372 |
Method for making a semiconductor device with improved sidewall junction capacitance |
May 9, 2000 |
| A semiconductor device (10) of the present invention has a gate (32) insulatively disposed above the substrate, source and drain regions (36, 38) disposed near the surface in the substrate adjacent opposite sides of the gate (32), and a field oxide region (26) disposed in the surface of |
| 5942374 |
Integrated circuits formed in radiation sensitive material and method of forming same |
August 24, 1999 |
| A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 ma |
| 5917222 |
Intergrated circuit combining high frequency bipolar and high power CMOS transistors |
June 29, 1999 |
| A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxia |
| 5911104 |
Integrated circuit combining high frequency bipolar and high power CMOS transistors |
June 8, 1999 |
| A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxia |
| 5907171 |
Method of making floating-gate memory-cell array with digital logic transistors |
May 25, 1999 |
| A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvo |
| 5874849 |
Low voltage, high current pump for flash memory |
February 23, 1999 |
| A charge pump 1 for operation in an integrated circuit having a power source Vdd. The pump is made of a plurality of pump cells 10 connected together. Each pump cell includes an inverter 50 having a port 42 to receive a negative bias input, a port 44 to receive a positive bias input, |
| 5844839 |
Programmable and convertible non-volatile memory array |
December 1, 1998 |
| A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 |
| 5815026 |
High efficiency, high voltage, low current charge pump |
September 29, 1998 |
| An integrated circuit voltage multiplier 30 in a semiconductor substrate of a first conductivity type. The multiplier includes a diode 22, having a first voltage VDD applied to a first port thereof, the diode being made of: 1) a first well 12 of a second conductivity type formed in the |
| 5811850 |
LDMOS transistors, systems and methods |
September 22, 1998 |
| A process for the fabrication of an improved LDMOS transistor, and such an improved LDMOS transistor are provided. The improved LDMOS transistor is in a semiconductor layer of a first conductivity type. The transistor has a source and drain of a second conductivity type (opposite the fir |
| 5801091 |
Method for current ballasting and busing over active device area using a multi-level conductor p |
September 1, 1998 |
| The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting a |
| 5798649 |
Method for detecting defects in semiconductor insulators |
August 25, 1998 |
| The reliability of thin film insulators is determined with noise measurements which find the barrier height mean and standard deviation. A constant voltage source is applied across the thin film insulator. A low noise amplifier is connected across a resistor which is in series with the |
| 5798281 |
Method for stressing oxide in MOS devices during fabrication using first and second opposite pot |
August 25, 1998 |
| A method and apparatus are disclosed for stressing the oxide layer (36) of an MOS integrated circuit during the fabrication process. One aspect of the invention is a method for fabricating an MOS integrated circuit. In accordance with this method, an oxide layer (36) is formed on a s |
| 5767551 |
Intergrated circuit combining high frequency bipolar and high power CMOS transistors |
June 16, 1998 |
| A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxia |
| 5732021 |
Programmable and convertible non-volatile memory array |
March 24, 1998 |
| A method for selectibly erasing one or more non-volatile programmable memory cells in an integrated circuit. The method is applicable to an array 1 of memory cells 10 fabricated in a semiconductor substrate 30 of a first conductivity type semiconductor material, each cell having a fl |
| 5717634 |
Programmable and convertible non-volatile memory array |
February 10, 1998 |
| A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 |
| 5715195 |
Programmable memory verify "0" and verify "1" circuit and method |
February 3, 1998 |
| A method for automatically detecting and correcting the underprogramming of a memory cell 10 in a non-volatile, progrommable memory array 1, the array having a plurality of such cells, each such cell being programmable by a progromming step that stores charge therein and being erasable b |
| 5703807 |
EEPROM with enhanced reliability by selectable V.sub.PP for write and erase |
December 30, 1997 |
| A circuit and method for generating an erasure voltage and a programming voltage for an EEPROM array, the cells of the EEPROM array being capable of erasure and programming. A signal having an increasing voltage is generated. That signal is monitored, and the increase in voltage of said |
| 5691089 |
Integrated circuits formed in radiation sensitive material and method of forming same |
November 25, 1997 |
| A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 ma |
| 5689428 |
Integrated circuits, transistors, data processing systems, printed wiring boards, digital comput |
November 18, 1997 |
| An integrated circuit includes conductive elements and a radiation sensitive material interposed between the conductive elements and dosed to different conductivities in different portions thereof. Another aspect is a process of integrated circuit fabrication including steps of depositin |
| 5681768 |
Transistor having reduced hot carrier implantation |
October 28, 1997 |
| A transistor having reduced hot carrier implantation is disclosed which is formed on an outer surface (12) of a semiconductor substrate (10). The transistor comprises a source region (22) and a drain region (24) which define there between a channel region (34). A gate insulator layer (14 |
| 5679968 |
Transistor having reduced hot carrier implantation |
October 21, 1997 |
| A transistor having reduced hot carrier implantation is disclosed which is formed on an outer surface (12) of a semiconductor substrate (10). The transistor comprises a source region (22) and a drain region (24) which define there between a channel region (34). A gate insulator layer (14 |
| 5677041 |
Integrated circuits formed in radiation sensitive material and method of forming same |
October 14, 1997 |
| A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 ma |
| 5665991 |
Device having current ballasting and busing over active area using a multi-level conductor proce |
September 9, 1997 |
| The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting a |
| 5656517 |
Windowed source and segmented backgate contact linear geometry source cell for power DMOS proces |
August 12, 1997 |
| A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of |
| 5648275 |
Method for detecting defects in semiconductor insulators |
July 15, 1997 |
| The reliability of thin film insulators is determined with noise measurements which find the barrier height mean and standard deviation. A constant voltage source is applied across the thin film insulator. A low noise amplifier is connected across a resistor which is in series with the |
| 5642295 |
Systems utilizing a single chip microcontroller having non-volatile memory devices and power dev |
June 24, 1997 |
| An embodiment of the instant invention is a system for displaying information related to the performance of an automobile, the system comprising: a power supply; a display means, the display means includes gauges; a plurality of sensors for providing data; and a microcontroller for r |
| 5598102 |
Method for detecting defects in semiconductor insulators |
January 28, 1997 |
| The reliability of thin film insulators is determined with noise measurements which find the barrier height mean and standard deviation. A constant voltage source is applied across the thin film insulator. A low noise amplifier is connected across a resistor which is in series with the |
| 5589697 |
Charge pump circuit with capacitors |
December 31, 1996 |
| A charge pump (10) uses Schottky diodes (12) coupled to clock signals (.phi..sub.1 and .phi..sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16). |
| 5585657 |
Windowed and segmented linear geometry source cell for power DMOS processes |
December 17, 1996 |
| A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of |
| 5585294 |
Method of fabricating lateral double diffused MOS (LDMOS) transistors |
December 17, 1996 |
| A process for the fabrication of an improved LDMOS transistor, and such an improved LDMOS transistor are provided. The improved LDMOS transistor is in a semiconductor layer of a first conductivity type. The transistor has a source and drain of a second conductivity type (opposite the fir |
| 5567550 |
Method of making a mask for making integrated circuits |
October 22, 1996 |
| A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 ma |
| 5557569 |
Low voltage flash EEPROM C-cell using fowler-nordheim tunneling |
September 17, 1996 |
| A low voltage flash EEPROM X-Cell includes an array of memory cell transistors (24) that constitute asymmetric floating gate memory cells wherein programming is achieved on only one side of the memory cells (24). The programming side of each of the memory cells (24) is connected to one |
| 5515319 |
Non-volatile memory cell and level shifter |
May 7, 1996 |
| A non-volatile memory cell 10 is disclosed herein. The cell is formed in a first semiconductor region 12 of a first conductivity type. A second semiconductor region 14 of a second conductivity type formed over the first semiconductor region 12. A third semiconductor region 16 of the |
| 5504708 |
Flash EEPROM array with P-tank insulated from substrate by deep N-tank |
April 2, 1996 |
| In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allo |
| 5504706 |
Low voltage Fowler-Nordheim flash EEPROM memory array utilizing single level poly cells |
April 2, 1996 |
| A memory array (10) is provided with a plurality of Flash EEPROM memory cells (24) that are fabricated with a single level poly process. Each of the transistor cells (24) is fabricated from a single poly layer floating gate (40) that extends between a moat region (30) and an implanted re |
| 5504451 |
Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semicond |
April 2, 1996 |
| An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (556/403); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (557, 405) for the gating of an EEPROM memory |
| 5500548 |
Non-epitaxial CMOS structures and processors |
March 19, 1996 |
| An integrated circuit device (10) is provided that comprises an P-FET (12) and an N-FET (14) formed on a semiconductor substrate (32). The P-FET (12) is formed in an n- tank (46). The source (18) and back-gate contact (22) of the P-FET (12) are connected to the V.sub.DD supply voltage. A |
| 5500392 |
Planar process using common alignment marks for well implants |
March 19, 1996 |
| A preferred embodiment of the present invention is a method of forming a device on a semiconductor substrate of a first conductivity type, the method comprising: forming a semiconducting layer on the substrate; etching alignment marks in the semiconducting layer (102); forming a first |
| 5491105 |
LDMOS transistor with self-aligned source/backgate and photo-aligned gate |
February 13, 1996 |
| An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tan |
| 5479040 |
Charge pump circuit with field oxide regions |
December 26, 1995 |
| A charge pump (10) uses Schottky diodes (12) coupled to clock signals (o.sub.1 and o.sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16). |
| 5467307 |
Memory array utilizing low voltage Fowler-Nordheim Flash EEPROM cell |
November 14, 1995 |
| A Flash EEPROM memory array includes a plurality of transistor memory cells (24) arranged in rows and columns. The sources of the transistors (24) are connected to Virtual Ground Lines (29) and the drains thereof are connected to Column Lines (28). The memory cells (24) are programmable |
| 5432740 |
Low voltage flash EEPROM memory cell with merge select transistor and non-stacked gate structure |
July 11, 1995 |
| A EEPROM memory array (10) includes a plurality of memory cells (24) which are connected in a symmetric array between row lines (26) and Column Lines (28) and Virtual Ground Lines (29). Each of the memory cells includes a merged pass gate which is connected to a control gate. A non-stack |
| 5429959 |
Process for simultaneously fabricating a bipolar transistor and a field-effect transistor |
July 4, 1995 |
| A bipolar transistor (408) is formed at a face of a semiconductor layer (152) of a first conductivity type. A first tank region (410) is formed in the semiconductor layer to be of a second conductivity type. A second tank region (412) is formed in the self-conductor layer to be of the fi |
| 5411908 |
Flash EEPROM array with P-tank insulated from substrate by deep N-tank |
May 2, 1995 |
| In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allo |
| 5407844 |
Process for simultaneously fabricating an insulated gate field-effect transistor and a bipolar t |
April 18, 1995 |
| An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to |
| 5382536 |
Method of fabricating lateral DMOS structure |
January 17, 1995 |
| A lateral DMOS (LDMOS) transistor 10 is disclosed herein. In one embodiment, an n doped silicon layer 14 is provided and a field oxide region 24 is formed therein. A p doped D-well region 20 is formed in the silicon layer 14 and includes a p doped shallow, extension region 22 which e |
| 5364801 |
Method of forming a charge pump circuit |
November 15, 1994 |
| A charge pump (10) uses Schottky diodes (12) coupled to clock signals (.phi..sub.1 and .phi..sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16). |
| 5355007 |
Devices for non-volatile memory, systems and methods |
October 11, 1994 |
| An electrically-erasable, electrically-programmable read-only memory cell is formed in a layer of semiconductor (1062) of a first conductivity type. A first heavily doped region (1022) and a second heavily doped region (1024) are formed in semiconductor layer (1062) to be of a second |
