| Patent Number |
Title Of Patent |
Date Issued |
| 7610476 |
Multiple control sequences per row of microcode ROM |
October 27, 2009 |
| Various embodiments of methods and systems for storing multiple groups of microcode operations and corresponding control sequences per row of microcode ROM are disclosed. In one embodiment, an integrated circuit may include a microcode ROM coupled to a control sequence logic unit. The |
| 7555633 |
Instruction cache prefetch based on trace cache eviction |
June 30, 2009 |
| Various embodiments of methods and systems for implementing a microprocessor that fetches a group of instructions into instruction cache in response to a corresponding trace being evicted from the trace cache are disclosed. In some embodiments, a microprocessor may include an instruc |
| 7213126 |
Method and processor including logic for storing traces within a trace cache |
May 1, 2007 |
| A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be associated with a res |
| 7133969 |
System and method for handling exceptional instructions in a trace cache based processor |
November 7, 2006 |
| A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache |
| 6976122 |
Dynamic idle counter threshold value for use in memory paging policy |
December 13, 2005 |
| A memory controller includes a threshold register that stores a value indicating a length of time and a control unit. In response to a first memory access request, the control unit generates signals that cause a memory device to open a page of memory. The control unit generates signals |
