| Patent Number |
Title Of Patent |
Date Issued |
| 7443385 |
Data processing |
October 28, 2008 |
| Data processing apparatus comprises an array of user-operable controls, the controls being adjustable by movement of a user's hand while touching a control; a detector for detecting when a user's hand is touching a control; a display screen for displaying respective screen icons asso |
| 7003358 |
Audio signal processors |
February 21, 2006 |
| An audio signal processor which modifies audio signal components outside the conventional audio frequency band. The processor includes a Delta Sigma Modulator (DSM) that receives a non-interpolated digital audio signal sampled at a frequency of at least 198 kHz. |
| 6970753 |
Storage and transmission of one-bit data |
November 29, 2005 |
| Apparatus for storing or transmitting a one-bit digital signal comprises an input inverter for inverting a subset of the data bits of an input one-bit digital signal, to generate a bit-inverted signal; a storage or transmission medium for storing or transmitting the bit-inverted signal; |
| 6604009 |
Signal processors |
August 5, 2003 |
| A signal processor for 1-bit signals comprises a fifth order Delta-Sigma Modulator (DSM) having an input for receiving a 1-bit signal and an output at which a processed 1-bit signal is produced by a quantizer. The quantizer receives a p-bit signal from a series of five signal integration |
| 6593866 |
Signal processors |
July 15, 2003 |
| A differential microphone (50) produces a differential pair of output signals which are applied by a differential analogue amplifier (52). The amplified differential signals are converted to 1-bit form by a pair of analogue to digital converters (54, 55) and are combined in a 1-bit Delta |
| 6577910 |
Digital audio signal processors |
June 10, 2003 |
| A digital audio signal processor processes digital audio signals having a first sampling rate S1. The processor has a multiplicity of manually adjustable controls (403) for setting desired parameters of signals to be processed. Sampling means (404) sample each control (403) setting at a |
| 6377193 |
System for converting between non-logarithmic values and logarithmic values |
April 23, 2002 |
| An audio signal processor for processing 1-bit signals, comprises an input 40 for receiving a 1-bit signal, means 41, 42 for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n is greater than one, means 43 fo |
| 6295014 |
System for processing one-bit audio signals |
September 25, 2001 |
| An audio signal processor for processing 1-bit signals, comprises an input 40 for receiving a 1-bit signal, means 41, 42 for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n is greater than one, means 43 fo |
| 6286020 |
Signal processor delta-sigma modulator stage |
September 4, 2001 |
| A 1-bit nth order Delta Sigma Modulator where n is at least one comprises a linear signal processing section (50) which processes the 1-bit signal and produces a p bit output, a filter (52) which filters the p bit signal, an adder (53) a quantizer Q coupled to the output of the adder (53 |
| 6281885 |
Audio processing |
August 28, 2001 |
| Audio processing apparatus comprises an audio processor operable to apply one or more processing operations from a set of audio processing operations to an input audio signal; adjustment controls for adjusting processing parameters associated with each of the set of processing operat |
| 6188344 |
Signal processors |
February 13, 2001 |
| A 1-bit signal processor receives a 1-bit signal having a first sampling rate eg 64 fs. An upconverter (41) increases the sampling rate to eg 128 fs. A series of Delta Sigma Modulators (42, 43) processes the signal. The processed signal is down-converted by a converter (44) to 64 fs. As |
| 6175322 |
Signal processors for one bit signals |
January 16, 2001 |
| A signal processor for 1-bit signals comprises an nth order D Sigma Modulator (DSM) having an input (4) for receiving a 1-bit signal and an output (5) at which a processed 1-bit signal is produced by a quantizer (Q). The quantizer (Q) receives a p-bit signal from a series of 5 signal |
| 6167100 |
Digital signal processing |
December 26, 2000 |
| One-bit digital signal processing apparatus for generating an output one-bit signal by switching from a first to a second one-bit signal in response to a detection that m consecutive bits of the first and second signal are identical, the apparatus comprising means for varying m in de |
| 6144328 |
Cascaded delta sigma modulators |
November 7, 2000 |
| A signal processor for processing 1-bit signals comprising at least a pair of Delta Sigma Modulators (DSM) coupled in series, one of the said pair of DSMs having an signal-band noise-shaping filter characteristic complementary to the signal-band noise-shaping filter characteristic of |
| 6061007 |
1-bit signal processing system |
May 9, 2000 |
| A 1-bit signal (44) is compressed (40, 41) by dividing it into a series of n-bit words and encoding the words according to the probability of their occurrence. |
| 6057792 |
Signal processors |
May 2, 2000 |
| An nth order Delta Sigma Modulator (DSM) where n.gtoreq.1, comprising an input (4) for receiving a 1-bit input signal having a signal component and a noise component,a quantifier (Q) for re-quantizing a p-bit signal (where p>1) to 1-bit form, the re-quantised 1-bit signal being the ou |
| 5983258 |
Apparatus and method for summing 1-bit signals |
November 9, 1999 |
| An arithmetic stage calculates the sum AX+BY where A and B are 1-bit signals and X and Y p bit coefficients X=7 and Y=3 and the corresponding bits b.sub.1 to b.sub.5 are represented together with the corresponding logical states of A and B. It will be seen that for example column b.sub.3 |
